Lines Matching +full:pre +full:- +full:emphasis
1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <generic-phy.h>
24 #include <linux/usb/phy-rockchip-usbdp.h>
51 * struct reg_sequence - An individual write from a sequence of writes.
67 /* u2phy-grf */
71 /* usb-grf */
75 /* usbdpphy-grf */
125 bool hs; /* flag for high-speed */
143 /* voltage swing 0, pre-emphasis 0->3 */
151 /* voltage swing 1, pre-emphasis 0->2 */
158 /* voltage swing 2, pre-emphasis 0->1 */
164 /* voltage swing 3, pre-emphasis 0 */
171 /* voltage swing 0, pre-emphasis 0->3 */
179 /* voltage swing 1, pre-emphasis 0->2 */
186 /* voltage swing 2, pre-emphasis 0->1 */
192 /* voltage swing 3, pre-emphasis 0 */
199 /* voltage swing 0, pre-emphasis 0->3 */
207 /* voltage swing 1, pre-emphasis 0->2 */
214 /* voltage swing 2, pre-emphasis 0->1 */
220 /* voltage swing 3, pre-emphasis 0 */
306 tmp = en ? reg->enable : reg->disable; in grfreg_write()
307 mask = GENMASK(reg->bitend, reg->bitstart); in grfreg_write()
308 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in grfreg_write()
310 return regmap_write(base, reg->offset, val); in grfreg_write()
335 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_reset_init()
339 udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, in udphy_reset_init()
340 sizeof(*udphy->rsts), GFP_KERNEL); in udphy_reset_init()
341 if (!udphy->rsts) in udphy_reset_init()
342 return -ENOMEM; in udphy_reset_init()
344 for (idx = 0; idx < cfg->num_rsts; idx++) { in udphy_reset_init()
345 const char *name = cfg->rst_list[idx]; in udphy_reset_init()
347 ret = reset_get_by_name(dev, name, &udphy->rsts[idx]); in udphy_reset_init()
353 reset_assert(&udphy->rsts[idx]); in udphy_reset_init()
359 devm_kfree(dev, udphy->rsts); in udphy_reset_init()
372 return -EINVAL; in udphy_get_rst_idx()
377 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_reset_assert()
380 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); in udphy_reset_assert()
384 return reset_assert(&udphy->rsts[idx]); in udphy_reset_assert()
389 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_reset_deassert()
392 idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); in udphy_reset_deassert()
396 return reset_deassert(&udphy->rsts[idx]); in udphy_reset_deassert()
401 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_u3_port_disable()
404 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; in udphy_u3_port_disable()
405 grfreg_write(udphy->usbgrf, preg, disable); in udphy_u3_port_disable()
411 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_usb_bvalid_enable()
413 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); in udphy_usb_bvalid_enable()
414 grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); in udphy_usb_bvalid_enable()
420 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
421 * ---------------------------------------------------------------------------
422 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3
432 * ---------------------------------------------------------------------------
435 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
437 * ---------------------------------------------------------------------------
438 * B11-B10 A2-A3 A11-A10 B2-B3
439 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
442 * ---------------------------------------------------------------------------
443 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
445 * ---------------------------------------------------------------------------
446 * B11-B10 A2-A3 A11-A10 B2-B3
447 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx)
450 * ---------------------------------------------------------------------------
454 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_dplane_select()
456 if (cfg->dplane_select) in udphy_dplane_select()
457 return cfg->dplane_select(udphy); in udphy_dplane_select()
466 switch (udphy->mode) { in udphy_dplane_get()
485 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_dplane_enable()
488 if (cfg->dplane_enable) in udphy_dplane_enable()
489 ret = cfg->dplane_enable(udphy, dp_lanes); in udphy_dplane_enable()
498 if (udphy->flip) { in upphy_set_typec_default_mapping()
499 udphy->dp_lane_sel[0] = 0; in upphy_set_typec_default_mapping()
500 udphy->dp_lane_sel[1] = 1; in upphy_set_typec_default_mapping()
501 udphy->dp_lane_sel[2] = 3; in upphy_set_typec_default_mapping()
502 udphy->dp_lane_sel[3] = 2; in upphy_set_typec_default_mapping()
503 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; in upphy_set_typec_default_mapping()
504 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; in upphy_set_typec_default_mapping()
505 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; in upphy_set_typec_default_mapping()
506 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; in upphy_set_typec_default_mapping()
507 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; in upphy_set_typec_default_mapping()
508 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; in upphy_set_typec_default_mapping()
510 udphy->dp_lane_sel[0] = 2; in upphy_set_typec_default_mapping()
511 udphy->dp_lane_sel[1] = 3; in upphy_set_typec_default_mapping()
512 udphy->dp_lane_sel[2] = 1; in upphy_set_typec_default_mapping()
513 udphy->dp_lane_sel[3] = 0; in upphy_set_typec_default_mapping()
514 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; in upphy_set_typec_default_mapping()
515 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; in upphy_set_typec_default_mapping()
516 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; in upphy_set_typec_default_mapping()
517 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; in upphy_set_typec_default_mapping()
518 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; in upphy_set_typec_default_mapping()
519 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; in upphy_set_typec_default_mapping()
522 udphy->mode = UDPHY_MODE_DP_USB; in upphy_set_typec_default_mapping()
529 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_setup()
532 if (cfg->combophy_init) { in udphy_setup()
533 ret = cfg->combophy_init(udphy); in udphy_setup()
535 dev_err(udphy->dev, "failed to init combophy\n"); in udphy_setup()
543 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in udphy_disable()
546 for (i = 0; i < cfg->num_rsts; i++) in udphy_disable()
547 reset_assert(&udphy->rsts[i]); in udphy_disable()
554 const struct device_node *np = ofnode_to_np(dev->node); in udphy_parse_lane_mux_data()
558 prop = of_find_property(np, "rockchip,dp-lane-mux", &len); in udphy_parse_lane_mux_data()
561 udphy->mode = UDPHY_MODE_USB; in udphy_parse_lane_mux_data()
569 return -EINVAL; in udphy_parse_lane_mux_data()
572 ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes); in udphy_parse_lane_mux_data()
575 return -EINVAL; in udphy_parse_lane_mux_data()
581 if (udphy->dp_lane_sel[i] > 3) { in udphy_parse_lane_mux_data()
583 return -EINVAL; in udphy_parse_lane_mux_data()
586 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; in udphy_parse_lane_mux_data()
589 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { in udphy_parse_lane_mux_data()
591 return -EINVAL; in udphy_parse_lane_mux_data()
596 udphy->mode = UDPHY_MODE_DP; in udphy_parse_lane_mux_data()
598 udphy->mode |= UDPHY_MODE_USB; in udphy_parse_lane_mux_data()
599 udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false; in udphy_parse_lane_mux_data()
610 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,u2phy-grf"); in udphy_parse_dt()
611 if (IS_ERR(udphy->u2phygrf)) { in udphy_parse_dt()
612 if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { in udphy_parse_dt()
613 dev_warn(dev, "missing u2phy-grf dt node\n"); in udphy_parse_dt()
614 udphy->u2phygrf = NULL; in udphy_parse_dt()
616 return PTR_ERR(udphy->u2phygrf); in udphy_parse_dt()
620 udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usbdpphy-grf"); in udphy_parse_dt()
621 if (IS_ERR(udphy->udphygrf)) { in udphy_parse_dt()
622 if (PTR_ERR(udphy->udphygrf) == -ENODEV) { in udphy_parse_dt()
623 dev_warn(dev, "missing usbdpphy-grf dt node\n"); in udphy_parse_dt()
624 udphy->udphygrf = NULL; in udphy_parse_dt()
626 return PTR_ERR(udphy->udphygrf); in udphy_parse_dt()
630 udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,usb-grf"); in udphy_parse_dt()
631 if (IS_ERR(udphy->usbgrf)) { in udphy_parse_dt()
632 if (PTR_ERR(udphy->usbgrf) == -ENODEV) { in udphy_parse_dt()
633 dev_warn(dev, "missing usb-grf dt node\n"); in udphy_parse_dt()
634 udphy->usbgrf = NULL; in udphy_parse_dt()
636 return PTR_ERR(udphy->usbgrf); in udphy_parse_dt()
640 udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf"); in udphy_parse_dt()
641 if (IS_ERR(udphy->vogrf)) { in udphy_parse_dt()
642 if (PTR_ERR(udphy->vogrf) == -ENODEV) { in udphy_parse_dt()
643 dev_warn(dev, "missing vo-grf dt node\n"); in udphy_parse_dt()
644 udphy->vogrf = NULL; in udphy_parse_dt()
646 return PTR_ERR(udphy->vogrf); in udphy_parse_dt()
654 if (dev_read_prop(dev, "maximum-speed", NULL)) { in udphy_parse_dt()
655 maximum_speed = usb_get_maximum_speed(dev->node); in udphy_parse_dt()
656 udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; in udphy_parse_dt()
674 if (!(udphy->mode & mode)) { in udphy_power_on()
675 printf("%s: mode 0x%02x is not support\n", udphy->dev->name, in udphy_power_on()
677 return -EINVAL; in udphy_power_on()
680 if (udphy->status == UDPHY_MODE_NONE) { in udphy_power_on()
681 udphy->mode_change = false; in udphy_power_on()
686 if (udphy->mode & UDPHY_MODE_USB) in udphy_power_on()
688 } else if (udphy->mode_change) { in udphy_power_on()
689 udphy->mode_change = false; in udphy_power_on()
690 udphy->status = UDPHY_MODE_NONE; in udphy_power_on()
691 if (udphy->mode == UDPHY_MODE_DP) in udphy_power_on()
702 udphy->status |= mode; in udphy_power_on()
711 if (!(udphy->mode & mode)) { in udphy_power_off()
712 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); in udphy_power_off()
716 if (!udphy->status) in udphy_power_off()
719 udphy->status &= ~mode; in udphy_power_off()
721 if (udphy->status == UDPHY_MODE_NONE) { in udphy_power_off()
732 struct udevice *parent = phy->dev->parent; in rockchip_dpphy_power_on()
737 phy->attrs.bus_width = dp_lanes; in rockchip_dpphy_power_on()
738 phy->attrs.max_link_rate = udphy->max_link_rate; in rockchip_dpphy_power_on()
753 struct udevice *parent = phy->dev->parent; in rockchip_dpphy_power_off()
770 if (dp->set_rate) { in rockchip_dpphy_verify_config()
771 switch (dp->link_rate) { in rockchip_dpphy_verify_config()
779 return -EINVAL; in rockchip_dpphy_verify_config()
784 switch (dp->lanes) { in rockchip_dpphy_verify_config()
791 return -EINVAL; in rockchip_dpphy_verify_config()
795 * If changing voltages is required, check swing and pre-emphasis in rockchip_dpphy_verify_config()
796 * levels, per-lane. in rockchip_dpphy_verify_config()
798 if (dp->set_voltages) { in rockchip_dpphy_verify_config()
800 for (i = 0; i < dp->lanes; i++) { in rockchip_dpphy_verify_config()
801 if (dp->voltage[i] > 3 || dp->pre[i] > 3) in rockchip_dpphy_verify_config()
802 return -EINVAL; in rockchip_dpphy_verify_config()
805 * Sum of voltage swing and pre-emphasis levels cannot in rockchip_dpphy_verify_config()
808 if (dp->voltage[i] + dp->pre[i] > 3) in rockchip_dpphy_verify_config()
809 return -EINVAL; in rockchip_dpphy_verify_config()
819 struct udevice *parent = phy->dev->parent; in rockchip_dpphy_configure()
821 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in rockchip_dpphy_configure()
824 ret = rockchip_dpphy_verify_config(udphy, &opts->dp); in rockchip_dpphy_configure()
828 if (opts->dp.set_rate && cfg->dp_phy_set_rate) { in rockchip_dpphy_configure()
829 ret = cfg->dp_phy_set_rate(udphy, &opts->dp); in rockchip_dpphy_configure()
832 udphy->dev->name); in rockchip_dpphy_configure()
837 if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) { in rockchip_dpphy_configure()
838 ret = cfg->dp_phy_set_voltages(udphy, &opts->dp); in rockchip_dpphy_configure()
841 udphy->dev->name); in rockchip_dpphy_configure()
857 struct udevice *parent = phy->dev->parent; in rockchip_u3phy_init()
860 /* DP only or high-speed, disable U3 port */ in rockchip_u3phy_init()
861 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { in rockchip_u3phy_init()
871 struct udevice *parent = phy->dev->parent; in rockchip_u3phy_exit()
874 /* DP only or high-speed */ in rockchip_u3phy_exit()
875 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) in rockchip_u3phy_exit()
896 pr_err("%s: get u3-port failed: %d\n", __func__, ret); in rockchip_u3phy_uboot_init()
900 /* DP only or high-speed, disable U3 port */ in rockchip_u3phy_uboot_init()
901 udphy = dev_get_priv(udev->parent); in rockchip_u3phy_uboot_init()
902 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { in rockchip_u3phy_uboot_init()
912 const struct device_node *np = ofnode_to_np(dev->node); in rockchip_udphy_probe()
917 udphy->dev = dev; in rockchip_udphy_probe()
922 udphy->id = id; in rockchip_udphy_probe()
927 return -EINVAL; in rockchip_udphy_probe()
929 udphy->cfgs = phy_cfgs; in rockchip_udphy_probe()
931 ret = regmap_init_mem(dev, &udphy->pma_regmap); in rockchip_udphy_probe()
934 udphy->pma_regmap->base += UDPHY_PMA; in rockchip_udphy_probe()
952 printf("%s: no subnode for %s\n", __func__, parent->name); in rockchip_udphy_bind()
953 return -ENXIO; in rockchip_udphy_bind()
959 if (!strcasecmp(node_name, "u3-port")) { in rockchip_udphy_bind()
968 } else if (!strcasecmp(node_name, "dp-port")) { in rockchip_udphy_bind()
988 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg, in rk3588_udphy_refclk_set()
1002 if (udphy->mode & UDPHY_MODE_USB) { in rk3588_udphy_status_check()
1003 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, in rk3588_udphy_status_check()
1007 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); in rk3588_udphy_status_check()
1012 if (udphy->mode & UDPHY_MODE_USB) { in rk3588_udphy_status_check()
1013 if (!udphy->flip) { in rk3588_udphy_status_check()
1014 ret = regmap_read_poll_timeout(udphy->pma_regmap, in rk3588_udphy_status_check()
1019 dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); in rk3588_udphy_status_check()
1021 ret = regmap_read_poll_timeout(udphy->pma_regmap, in rk3588_udphy_status_check()
1026 dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); in rk3588_udphy_status_check()
1035 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in rk3588_udphy_init()
1039 if (udphy->mode & UDPHY_MODE_USB) in rk3588_udphy_init()
1040 grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); in rk3588_udphy_init()
1043 grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); in rk3588_udphy_init()
1049 ret = __regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence, in rk3588_udphy_init()
1052 dev_err(udphy->dev, "init sequence set error %d\n", ret); in rk3588_udphy_init()
1058 dev_err(udphy->dev, "refclk set error %d\n", ret); in rk3588_udphy_init()
1063 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, in rk3588_udphy_init()
1065 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | in rk3588_udphy_init()
1066 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | in rk3588_udphy_init()
1067 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | in rk3588_udphy_init()
1068 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | in rk3588_udphy_init()
1072 if (udphy->mode & UDPHY_MODE_USB) in rk3588_udphy_init()
1075 if (udphy->mode & UDPHY_MODE_DP) { in rk3588_udphy_init()
1076 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, in rk3588_udphy_init()
1084 if (udphy->mode & UDPHY_MODE_USB) { in rk3588_udphy_init()
1113 val |= BIT(udphy->dp_lane_sel[i]); in rk3588_udphy_dplane_enable()
1115 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, in rk3588_udphy_dplane_enable()
1119 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, in rk3588_udphy_dplane_enable()
1129 switch (udphy->mode) { in rk3588_udphy_dplane_select()
1131 value |= 2 << udphy->dp_lane_sel[2] * 2; in rk3588_udphy_dplane_select()
1132 value |= 3 << udphy->dp_lane_sel[3] * 2; in rk3588_udphy_dplane_select()
1134 value |= 0 << udphy->dp_lane_sel[0] * 2; in rk3588_udphy_dplane_select()
1135 value |= 1 << udphy->dp_lane_sel[1] * 2; in rk3588_udphy_dplane_select()
1143 regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0, in rk3588_udphy_dplane_select()
1145 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | in rk3588_udphy_dplane_select()
1146 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); in rk3588_udphy_dplane_select()
1157 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, in rk3588_dp_phy_set_rate()
1160 switch (dp->link_rate) { in rk3588_dp_phy_set_rate()
1162 udphy->bw = DP_BW_RBR; in rk3588_dp_phy_set_rate()
1165 udphy->bw = DP_BW_HBR; in rk3588_dp_phy_set_rate()
1168 udphy->bw = DP_BW_HBR2; in rk3588_dp_phy_set_rate()
1171 udphy->bw = DP_BW_HBR3; in rk3588_dp_phy_set_rate()
1174 return -EINVAL; in rk3588_dp_phy_set_rate()
1177 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, in rk3588_dp_phy_set_rate()
1178 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); in rk3588_dp_phy_set_rate()
1179 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, in rk3588_dp_phy_set_rate()
1180 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); in rk3588_dp_phy_set_rate()
1181 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, in rk3588_dp_phy_set_rate()
1184 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, in rk3588_dp_phy_set_rate()
1197 u32 voltage, u32 pre, u32 lane) in rk3588_dp_phy_set_voltage() argument
1201 const struct rockchip_udphy_cfg *cfg = udphy->cfgs; in rk3588_dp_phy_set_voltage()
1204 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; in rk3588_dp_phy_set_voltage()
1205 val = dp_ctrl[voltage][pre].trsv_reg0204; in rk3588_dp_phy_set_voltage()
1206 regmap_write(udphy->pma_regmap, 0x0810 + offset, val); in rk3588_dp_phy_set_voltage()
1208 val = dp_ctrl[voltage][pre].trsv_reg0205; in rk3588_dp_phy_set_voltage()
1209 regmap_write(udphy->pma_regmap, 0x0814 + offset, val); in rk3588_dp_phy_set_voltage()
1211 val = dp_ctrl[voltage][pre].trsv_reg0206; in rk3588_dp_phy_set_voltage()
1212 regmap_write(udphy->pma_regmap, 0x0818 + offset, val); in rk3588_dp_phy_set_voltage()
1214 val = dp_ctrl[voltage][pre].trsv_reg0207; in rk3588_dp_phy_set_voltage()
1215 regmap_write(udphy->pma_regmap, 0x081c + offset, val); in rk3588_dp_phy_set_voltage()
1223 for (i = 0; i < dp->lanes; i++) { in rk3588_dp_phy_set_voltages()
1224 lane = udphy->dp_lane_sel[i]; in rk3588_dp_phy_set_voltages()
1225 switch (dp->link_rate) { in rk3588_dp_phy_set_voltages()
1228 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), in rk3588_dp_phy_set_voltages()
1231 udphy->lane_mux_sel[lane])); in rk3588_dp_phy_set_voltages()
1235 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), in rk3588_dp_phy_set_voltages()
1241 rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane); in rk3588_dp_phy_set_voltages()
1249 struct rockchip_udphy *udphy = dev_get_priv(dev->parent); in rockchip_dpphy_probe()
1252 max_link_rate = dev_read_u32_default(dev, "max-link-rate", 8100); in rockchip_dpphy_probe()
1260 dev_warn(dev, "invalid max-link-rate %d, using 8100\n", max_link_rate); in rockchip_dpphy_probe()
1265 udphy->max_link_rate = max_link_rate; in rockchip_dpphy_probe()
1278 /* u2phy-grf */
1282 /* usb-grf */
1286 /* usbdpphy-grf */
1305 .compatible = "rockchip,rk3588-usbdp-phy",