1 // SPDX-License-Identifier: GPL-2.0
3  * Rockchip PCIE3.0 phy driver
12 #include <generic-phy.h>
17 #include <reset-uclass.h>
65 	#include "phy-rockchip-snps-pcie3.fw"
73 	/* Deassert PCIe PMA output clamp mode */  in rockchip_p3phy_rk3568_init()
74 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,  in rockchip_p3phy_rk3568_init()
78 	if (priv->is_bifurcation) {  in rockchip_p3phy_rk3568_init()
79 		regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON6,  in rockchip_p3phy_rk3568_init()
81 		regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON1,  in rockchip_p3phy_rk3568_init()
85 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,  in rockchip_p3phy_rk3568_init()
87 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,  in rockchip_p3phy_rk3568_init()
89 	reset_deassert(&priv->p30phy);  in rockchip_p3phy_rk3568_init()
91 	ret = regmap_read_poll_timeout(priv->phy_grf,  in rockchip_p3phy_rk3568_init()
98 		return -ETIMEDOUT;  in rockchip_p3phy_rk3568_init()
101 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,  in rockchip_p3phy_rk3568_init()
104 		writel(phy_fw[i], priv->mmio + (i<<2));  in rockchip_p3phy_rk3568_init()
106 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,  in rockchip_p3phy_rk3568_init()
108 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,  in rockchip_p3phy_rk3568_init()
125 	/* Deassert PCIe PMA output clamp mode */  in rockchip_p3phy_rk3588_init()
126 	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,  in rockchip_p3phy_rk3588_init()
130 	if (priv->pcie30_phymode > 4)  in rockchip_p3phy_rk3588_init()
131 		priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;  in rockchip_p3phy_rk3588_init()
133 	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,  in rockchip_p3phy_rk3588_init()
134 		     (0x7<<16) | priv->pcie30_phymode);  in rockchip_p3phy_rk3588_init()
137 	reg = priv->pcie30_phymode & 3;  in rockchip_p3phy_rk3588_init()
139 		regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,  in rockchip_p3phy_rk3588_init()
143 	while (timeout--) {  in rockchip_p3phy_rk3588_init()
144 		regmap_read(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_STATUS1, &reg);  in rockchip_p3phy_rk3588_init()
152 		return -ETIMEDOUT;  in rockchip_p3phy_rk3588_init()
156 	while (timeout--) {  in rockchip_p3phy_rk3588_init()
157 		regmap_read(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_STATUS1, &reg);  in rockchip_p3phy_rk3588_init()
165 		return -ETIMEDOUT;  in rockchip_p3phy_rk3588_init()
168 	reset_deassert(&priv->p30phy);  in rockchip_p3phy_rk3588_init()
178 static int rochchip_p3phy_init(struct phy *phy)  in rochchip_p3phy_init()  argument
180 	struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);  in rochchip_p3phy_init()
183 	ret = clk_enable_bulk(&priv->clks);  in rochchip_p3phy_init()
189 	reset_assert(&priv->p30phy);  in rochchip_p3phy_init()
192 	if (priv->ops->phy_init) {  in rochchip_p3phy_init()
193 		ret = priv->ops->phy_init(priv);  in rochchip_p3phy_init()
195 			clk_disable_bulk(&priv->clks);  in rochchip_p3phy_init()
204 static int rochchip_p3phy_exit(struct phy *phy)  in rochchip_p3phy_exit()  argument
206 	struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);  in rochchip_p3phy_exit()
208 	clk_disable_bulk(&priv->clks);  in rochchip_p3phy_exit()
209 	reset_assert(&priv->p30phy);  in rochchip_p3phy_exit()
220 	priv->mmio = (void __iomem *)dev_read_addr(dev);  in rockchip_p3phy_probe()
221 	if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)  in rockchip_p3phy_probe()
222 		return -EINVAL;  in rockchip_p3phy_probe()
224 	priv->ops = (struct rockchip_p3phy_ops *)dev_get_driver_data(dev);  in rockchip_p3phy_probe()
225 	if (!priv->ops) {  in rockchip_p3phy_probe()
227 		return -EINVAL;  in rockchip_p3phy_probe()
231 					   "rockchip,phy-grf",  &syscon);  in rockchip_p3phy_probe()
233 		pr_err("unable to find syscon device for rockchip,phy-grf\n");  in rockchip_p3phy_probe()
237 	priv->phy_grf = syscon_get_regmap(syscon);  in rockchip_p3phy_probe()
238 	if (IS_ERR(priv->phy_grf)) {  in rockchip_p3phy_probe()
240 		return PTR_ERR(priv->phy_grf);  in rockchip_p3phy_probe()
243 	dev_dbg(priv->dev, "phy_grf is 0x%llx\n", priv->phy_grf->base);  in rockchip_p3phy_probe()
246 					   "rockchip,pipe-grf",  &syscon);  in rockchip_p3phy_probe()
249 		priv->pipe_grf = NULL;  in rockchip_p3phy_probe()
250 		pr_err("unable to get syscon device for rockchip,pipe-grf\n");  in rockchip_p3phy_probe()
254 	priv->pipe_grf = syscon_get_regmap(syscon);  in rockchip_p3phy_probe()
255 	if (IS_ERR(priv->pipe_grf))  in rockchip_p3phy_probe()
259 …priv->pcie30_phymode = dev_read_u32_default(dev, "rockchip,pcie30-phymode", PHY_MODE_PCIE_AGGREGAT…  in rockchip_p3phy_probe()
262 	ret = reset_get_by_name(dev, "phy", &priv->p30phy);  in rockchip_p3phy_probe()
264 		dev_err(dev, "no phy reset control specified\n");  in rockchip_p3phy_probe()
276 static int rockchip_p3phy_configure(struct phy *phy, union phy_configure_opts *opts)  in rockchip_p3phy_configure()  argument
278 	struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);  in rockchip_p3phy_configure()
280 	priv->is_bifurcation = opts->pcie.is_bifurcation;  in rockchip_p3phy_configure()
292 	{ .compatible = "rockchip,rk3568-pcie3-phy", .data = (ulong)&rk3568_ops},
293 	{ .compatible = "rockchip,rk3588-pcie3-phy", .data = (ulong)&rk3588_ops },