Lines Matching refs:cfg
83 const struct rockchip_combphy_cfg *cfg; member
102 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
103 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_pcie_init()
117 if (priv->cfg->combphy_cfg) { in rockchip_combphy_usb3_init()
118 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_usb3_init()
132 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sata_init()
133 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sata_init()
147 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sgmii_init()
148 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sgmii_init()
184 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init() local
197 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_init()
198 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); in rockchip_combphy_init()
211 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_exit() local
213 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_exit()
214 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); in rockchip_combphy_exit()
300 priv->cfg = phy_cfg; in rockchip_combphy_probe()
307 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3528_combphy_cfg() local
318 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3528_combphy_cfg()
319 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3528_combphy_cfg()
320 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3528_combphy_cfg()
321 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3528_combphy_cfg()
336 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3528_combphy_cfg()
337 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3528_combphy_cfg()
338 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3528_combphy_cfg()
345 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3528_combphy_cfg()
392 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg() local
403 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
404 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
405 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
406 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
442 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
443 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
444 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
445 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
453 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
516 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg() local
527 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
528 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
529 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
530 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
566 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
567 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
568 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
569 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
574 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
575 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
576 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
577 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
578 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
581 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
582 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
583 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
584 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
587 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
588 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
589 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
590 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
591 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
599 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
653 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg() local
658 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
659 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
660 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
661 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
700 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
701 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
702 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
713 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
714 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
715 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
716 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
717 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
718 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
729 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()