Lines Matching +full:ssc +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
12 #include <dt-bindings/phy/phy.h>
13 #include <generic-phy.h>
18 #include <reset-uclass.h>
75 u32 mode; member
91 tmp = en ? reg->enable : reg->disable; in param_write()
92 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
93 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
95 return regmap_write(base, reg->offset, val); in param_write()
102 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
103 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_pcie_init()
105 dev_err(priv->dev, "failed to init phy for pcie\n"); in rockchip_combphy_pcie_init()
117 if (priv->cfg->combphy_cfg) { in rockchip_combphy_usb3_init()
118 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_usb3_init()
120 dev_err(priv->dev, "failed to init phy for usb3\n"); in rockchip_combphy_usb3_init()
132 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sata_init()
133 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sata_init()
135 dev_err(priv->dev, "failed to init phy for sata\n"); in rockchip_combphy_sata_init()
147 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sgmii_init()
148 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sgmii_init()
150 dev_err(priv->dev, "failed to init phy for sgmii\n"); in rockchip_combphy_sgmii_init()
160 switch (priv->mode) { in rockchip_combphy_set_mode()
174 dev_err(priv->dev, "incompatible PHY type\n"); in rockchip_combphy_set_mode()
175 return -EINVAL; in rockchip_combphy_set_mode()
183 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); in rockchip_combphy_init()
184 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init()
187 ret = clk_enable(&priv->ref_clk); in rockchip_combphy_init()
188 if (ret < 0 && ret != -ENOSYS) in rockchip_combphy_init()
195 reset_deassert(&priv->phy_rst); in rockchip_combphy_init()
197 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_init()
198 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); in rockchip_combphy_init()
203 clk_disable(&priv->ref_clk); in rockchip_combphy_init()
210 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); in rockchip_combphy_exit()
211 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_exit()
213 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_exit()
214 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); in rockchip_combphy_exit()
216 reset_assert(&priv->phy_rst); in rockchip_combphy_exit()
217 clk_disable(&priv->ref_clk); in rockchip_combphy_exit()
224 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); in rockchip_combphy_xlate()
226 if (args->args_count != 1) { in rockchip_combphy_xlate()
228 return -EINVAL; in rockchip_combphy_xlate()
231 priv->mode = args->args[0]; in rockchip_combphy_xlate()
249 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); in rockchip_combphy_parse_dt()
251 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap ret= %d\n", ret); in rockchip_combphy_parse_dt()
254 priv->pipe_grf = syscon_get_regmap(syscon); in rockchip_combphy_parse_dt()
256 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); in rockchip_combphy_parse_dt()
258 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); in rockchip_combphy_parse_dt()
261 priv->phy_grf = syscon_get_regmap(syscon); in rockchip_combphy_parse_dt()
263 ret = clk_get_by_index(dev, 0, &priv->ref_clk); in rockchip_combphy_parse_dt()
266 return PTR_ERR(&priv->ref_clk); in rockchip_combphy_parse_dt()
269 ret = reset_get_by_name(dev, "combphy", &priv->phy_rst); in rockchip_combphy_parse_dt()
275 if (!dev_read_u32_array(dev, "rockchip,pcie1ln-sel-bits", in rockchip_combphy_parse_dt()
277 regmap_write(priv->pipe_grf, vals[0], in rockchip_combphy_parse_dt()
288 priv->mmio = (void __iomem *)dev_read_addr(udev); in rockchip_combphy_probe()
289 if (IS_ERR(priv->mmio)) in rockchip_combphy_probe()
290 return PTR_ERR(priv->mmio); in rockchip_combphy_probe()
295 return -EINVAL; in rockchip_combphy_probe()
298 priv->dev = udev; in rockchip_combphy_probe()
299 priv->mode = PHY_TYPE_SATA; in rockchip_combphy_probe()
300 priv->cfg = phy_cfg; in rockchip_combphy_probe()
307 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3528_combphy_cfg()
310 switch (priv->mode) { in rk3528_combphy_cfg()
312 /* Set SSC downward spread spectrum */ in rk3528_combphy_cfg()
313 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
316 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
318 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3528_combphy_cfg()
319 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3528_combphy_cfg()
320 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3528_combphy_cfg()
321 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3528_combphy_cfg()
324 /* Set SSC downward spread spectrum */ in rk3528_combphy_cfg()
325 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
328 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
331 val = readl(priv->mmio + 0x200); in rk3528_combphy_cfg()
334 writel(val, priv->mmio + 0x200); in rk3528_combphy_cfg()
336 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3528_combphy_cfg()
337 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3528_combphy_cfg()
338 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3528_combphy_cfg()
341 dev_err(priv->dev, "incompatible PHY type\n"); in rk3528_combphy_cfg()
342 return -EINVAL; in rk3528_combphy_cfg()
345 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3528_combphy_cfg()
346 if (priv->mode == PHY_TYPE_PCIE) { in rk3528_combphy_cfg()
348 val = readl(priv->mmio + 0x18); in rk3528_combphy_cfg()
351 writel(val, priv->mmio + 0x18); in rk3528_combphy_cfg()
354 val = readl(priv->mmio + 0x108); in rk3528_combphy_cfg()
357 writel(val, priv->mmio + 0x108); in rk3528_combphy_cfg()
364 /* pipe-phy-grf */
381 /* pipe-grf */
392 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg()
395 switch (priv->mode) { in rk3562_combphy_cfg()
397 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
398 val = readl(priv->mmio + (0x1f << 2)); in rk3562_combphy_cfg()
401 writel(val, priv->mmio + 0x7c); in rk3562_combphy_cfg()
403 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
404 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
405 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
406 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
409 /* Set SSC downward spread spectrum */ in rk3562_combphy_cfg()
410 val = readl(priv->mmio + (0x1f << 2)); in rk3562_combphy_cfg()
413 writel(val, priv->mmio + 0x7c); in rk3562_combphy_cfg()
416 val = readl(priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
419 writel(val, priv->mmio + (0x0e << 2)); in rk3562_combphy_cfg()
422 val = readl(priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
425 writel(val, priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
428 writel(0x4, priv->mmio + (0xb << 2)); in rk3562_combphy_cfg()
431 val = readl(priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
434 writel(val, priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
437 writel(0x32, priv->mmio + (0x11 << 2)); in rk3562_combphy_cfg()
440 writel(0xf0, priv->mmio + (0xa << 2)); in rk3562_combphy_cfg()
442 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
443 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
444 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
445 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
448 pr_err("%s, phy-type %d\n", __func__, priv->mode); in rk3562_combphy_cfg()
449 return -EINVAL; in rk3562_combphy_cfg()
452 clk_set_rate(&priv->ref_clk, 100000000); in rk3562_combphy_cfg()
453 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
455 if (priv->mode == PHY_TYPE_PCIE) { in rk3562_combphy_cfg()
457 val = readl(priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
460 writel(val, priv->mmio + (0x20 << 2)); in rk3562_combphy_cfg()
463 writel(0x4, priv->mmio + (0xb << 2)); in rk3562_combphy_cfg()
465 val = readl(priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
468 writel(val, priv->mmio + (0x5 << 2)); in rk3562_combphy_cfg()
470 writel(0x32, priv->mmio + (0x11 << 2)); in rk3562_combphy_cfg()
471 writel(0xf0, priv->mmio + (0xa << 2)); in rk3562_combphy_cfg()
474 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { in rk3562_combphy_cfg()
475 val = readl(priv->mmio + (0x7 << 2)); in rk3562_combphy_cfg()
477 writel(val, priv->mmio + (0x7 << 2)); in rk3562_combphy_cfg()
484 /* pipe-phy-grf */
505 /* pipe-grf */
516 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg()
519 switch (priv->mode) { in rk3568_combphy_cfg()
521 /* Set SSC downward spread spectrum */ in rk3568_combphy_cfg()
522 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
525 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
527 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
528 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
529 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
530 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
533 /* Set SSC downward spread spectrum */ in rk3568_combphy_cfg()
534 val = readl(priv->mmio + (0x1f << 2)); in rk3568_combphy_cfg()
537 writel(val, priv->mmio + 0x7c); in rk3568_combphy_cfg()
540 val = readl(priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
543 writel(val, priv->mmio + (0x0e << 2)); in rk3568_combphy_cfg()
546 val = readl(priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
549 writel(val, priv->mmio + (0x20 << 2)); in rk3568_combphy_cfg()
552 writel(0x4, priv->mmio + (0xb << 2)); in rk3568_combphy_cfg()
555 val = readl(priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
558 writel(val, priv->mmio + (0x5 << 2)); in rk3568_combphy_cfg()
561 writel(0x32, priv->mmio + (0x11 << 2)); in rk3568_combphy_cfg()
564 writel(0xf0, priv->mmio + (0xa << 2)); in rk3568_combphy_cfg()
566 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
567 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
568 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
569 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
572 writel(0x41, priv->mmio + 0x38); in rk3568_combphy_cfg()
573 writel(0x8F, priv->mmio + 0x18); in rk3568_combphy_cfg()
574 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
575 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
576 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
577 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
578 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
581 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
582 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
583 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
584 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
587 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
588 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
589 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
590 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
591 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
594 pr_err("%s, phy-type %d\n", __func__, priv->mode); in rk3568_combphy_cfg()
595 return -EINVAL; in rk3568_combphy_cfg()
599 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
601 if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { in rk3568_combphy_cfg()
602 val = readl(priv->mmio + (0x7 << 2)); in rk3568_combphy_cfg()
604 writel(val, priv->mmio + (0x7 << 2)); in rk3568_combphy_cfg()
611 /* pipe-phy-grf */
638 /* pipe-grf */
653 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg()
656 switch (priv->mode) { in rk3588_combphy_cfg()
658 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
659 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
660 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
661 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
664 /* Set SSC downward spread spectrum */ in rk3588_combphy_cfg()
665 val = readl(priv->mmio + (0x1f << 2)); in rk3588_combphy_cfg()
668 writel(val, priv->mmio + 0x7c); in rk3588_combphy_cfg()
671 val = readl(priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
674 writel(val, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
677 val = readl(priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
680 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
683 writel(0x4, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
686 val = readl(priv->mmio + (0x5 << 2)); in rk3588_combphy_cfg()
689 writel(val, priv->mmio + (0x5 << 2)); in rk3588_combphy_cfg()
692 writel(0x32, priv->mmio + (0x11 << 2)); in rk3588_combphy_cfg()
695 writel(0xf0, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
698 writel(0x0d, priv->mmio + (0x14 << 2)); in rk3588_combphy_cfg()
700 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
701 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
702 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
706 val = readl(priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
709 writel(val, priv->mmio + (0x0e << 2)); in rk3588_combphy_cfg()
711 writel(0x8F, priv->mmio + (0x06 << 2)); in rk3588_combphy_cfg()
713 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
714 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
715 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
716 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
717 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
718 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
723 dev_err(priv->dev, "incompatible PHY type\n"); in rk3588_combphy_cfg()
724 return -EINVAL; in rk3588_combphy_cfg()
728 clk_set_rate(&priv->ref_clk, 100000000); in rk3588_combphy_cfg()
729 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
730 if (priv->mode == PHY_TYPE_PCIE) { in rk3588_combphy_cfg()
732 val = readl(priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
735 writel(val, priv->mmio + (0x20 << 2)); in rk3588_combphy_cfg()
739 writel(val, priv->mmio + (0x1b << 2)); in rk3588_combphy_cfg()
743 writel(val, priv->mmio + (0xa << 2)); in rk3588_combphy_cfg()
745 writel(val, priv->mmio + (0xb << 2)); in rk3588_combphy_cfg()
747 writel(val, priv->mmio + (0xd << 2)); in rk3588_combphy_cfg()
754 /* pipe-phy-grf */
775 /* pipe-grf */
787 .compatible = "rockchip,rk3528-naneng-combphy",
791 .compatible = "rockchip,rk3562-naneng-combphy",
795 .compatible = "rockchip,rk3568-naneng-combphy",
799 .compatible = "rockchip,rk3588-naneng-combphy",
806 .name = "naneng-combphy",