105 			  struct rockchip_u3phy_port *u3phy_port,
335 				    struct rockchip_u3phy_port *u3phy_port,  in rockchip_u3phy_port_init()  argument
342 	mutex_init(&u3phy_port->mutex);  in rockchip_u3phy_port_init()
344 	u3phy_port->base = (void __iomem *)ofnode_get_addr(np_to_ofnode(child_np));  in rockchip_u3phy_port_init()
345 	if (IS_ERR(u3phy_port->base)) {  in rockchip_u3phy_port_init()
347 		return PTR_ERR(u3phy_port->base);  in rockchip_u3phy_port_init()
351 		u3phy_port->type = U3PHY_TYPE_PIPE;  in rockchip_u3phy_port_init()
352 		u3phy_port->refclk_25m_quirk =  in rockchip_u3phy_port_init()
356 		u3phy_port->type = U3PHY_TYPE_UTMI;  in rockchip_u3phy_port_init()
361 		ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);  in rockchip_u3phy_port_init()
423 		struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index];  in rockchip_u3phy_probe()  local
425 		u3phy_port->index = index;  in rockchip_u3phy_probe()
426 		ret = rockchip_u3phy_port_init(u3phy, u3phy_port,  in rockchip_u3phy_probe()
449 			       struct rockchip_u3phy_port *u3phy_port,  in rk3328_u3phy_tuning()  argument
452 	if (u3phy_port->type == U3PHY_TYPE_UTMI) {  in rk3328_u3phy_tuning()
476 		writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030);  in rk3328_u3phy_tuning()
477 		writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040);  in rk3328_u3phy_tuning()
478 		writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c);  in rk3328_u3phy_tuning()
479 	} else if (u3phy_port->type == U3PHY_TYPE_PIPE) {  in rk3328_u3phy_tuning()
480 		if (u3phy_port->refclk_25m_quirk) {  in rk3328_u3phy_tuning()
483 			writel(0x64, u3phy_port->base + 0x11c);  in rk3328_u3phy_tuning()
484 			writel(0x64, u3phy_port->base + 0x028);  in rk3328_u3phy_tuning()
485 			writel(0x01, u3phy_port->base + 0x020);  in rk3328_u3phy_tuning()
486 			writel(0x21, u3phy_port->base + 0x030);  in rk3328_u3phy_tuning()
487 			writel(0x06, u3phy_port->base + 0x108);  in rk3328_u3phy_tuning()
488 			writel(0x00, u3phy_port->base + 0x118);  in rk3328_u3phy_tuning()
491 			writel(0x80, u3phy_port->base + 0x10c);  in rk3328_u3phy_tuning()
492 			writel(0x01, u3phy_port->base + 0x118);  in rk3328_u3phy_tuning()
493 			writel(0x38, u3phy_port->base + 0x11c);  in rk3328_u3phy_tuning()
494 			writel(0x83, u3phy_port->base + 0x020);  in rk3328_u3phy_tuning()
495 			writel(0x02, u3phy_port->base + 0x108);  in rk3328_u3phy_tuning()
500 		writel(0x08, u3phy_port->base + 0x000);  in rk3328_u3phy_tuning()
501 		writel(0x0c, u3phy_port->base + 0x120);  in rk3328_u3phy_tuning()
504 		writel(0x70, u3phy_port->base + 0x150);  in rk3328_u3phy_tuning()
505 		writel(0x12, u3phy_port->base + 0x0c8);  in rk3328_u3phy_tuning()
506 		writel(0x05, u3phy_port->base + 0x148);  in rk3328_u3phy_tuning()
507 		writel(0x08, u3phy_port->base + 0x068);  in rk3328_u3phy_tuning()
508 		writel(0xf0, u3phy_port->base + 0x1c4);  in rk3328_u3phy_tuning()
509 		writel(0xff, u3phy_port->base + 0x070);  in rk3328_u3phy_tuning()
510 		writel(0x0f, u3phy_port->base + 0x06c);  in rk3328_u3phy_tuning()
511 		writel(0xe0, u3phy_port->base + 0x060);  in rk3328_u3phy_tuning()
518 		writel(0x08, u3phy_port->base + 0x180);  in rk3328_u3phy_tuning()