Lines Matching refs:u3phy
104 int (*phy_tuning)(struct rockchip_u3phy *u3phy,
185 struct rockchip_u3phy *u3phy = dev_get_priv(parent); in rockchip_u3phy_power_on() local
189 if (!u3phy->vbus_supply) { in rockchip_u3phy_power_on()
191 &u3phy->vbus_supply); in rockchip_u3phy_power_on()
197 ret = regulator_set_enable(u3phy->vbus_supply, true); in rockchip_u3phy_power_on()
210 struct rockchip_u3phy *u3phy = dev_get_priv(parent); in rockchip_u3phy_power_off() local
214 if (u3phy->vbus_supply) { in rockchip_u3phy_power_off()
215 ret = regulator_set_enable(u3phy->vbus_supply, false); in rockchip_u3phy_power_off()
221 u3phy->vbus_supply = NULL; in rockchip_u3phy_power_off()
275 static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy, in rockchip_u3phy_rest_deassert() argument
281 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n"); in rockchip_u3phy_rest_deassert()
283 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
284 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
290 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n"); in rockchip_u3phy_rest_deassert()
292 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
293 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
299 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n"); in rockchip_u3phy_rest_deassert()
301 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
302 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
306 static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy) in rockchip_u3phy_rest_assert() argument
310 dev_dbg(u3phy->dev, "assert u3phy reset\n"); in rockchip_u3phy_rest_assert()
312 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_assert()
313 reset_assert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_assert()
316 static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy, in rockchip_u3phy_parse_dt() argument
324 &u3phy->rsts[i]); in rockchip_u3phy_parse_dt()
334 static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy, in rockchip_u3phy_port_init() argument
340 dev_dbg(u3phy->dev, "u3phy port initialize\n"); in rockchip_u3phy_port_init()
346 dev_err(u3phy->dev, "failed to remap phy regs\n"); in rockchip_u3phy_port_init()
359 if (u3phy->cfgs->phy_tuning) { in rockchip_u3phy_port_init()
360 dev_dbg(u3phy->dev, "do u3phy tuning\n"); in rockchip_u3phy_port_init()
361 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); in rockchip_u3phy_port_init()
372 struct rockchip_u3phy *u3phy = dev_get_priv(udev); in rockchip_u3phy_probe() local
394 u3phy->dev = udev; in rockchip_u3phy_probe()
401 u3phy->cfgs = &phy_cfgs[index]; in rockchip_u3phy_probe()
407 if (!u3phy->cfgs) { in rockchip_u3phy_probe()
412 ret = rockchip_u3phy_parse_dt(u3phy, udev); in rockchip_u3phy_probe()
418 rockchip_u3phy_rest_assert(u3phy); in rockchip_u3phy_probe()
419 rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST); in rockchip_u3phy_probe()
423 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_probe()
426 ret = rockchip_u3phy_port_init(u3phy, u3phy_port, in rockchip_u3phy_probe()
438 rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST); in rockchip_u3phy_probe()
448 static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy, in rk3328_u3phy_tuning() argument
463 u3phy->apbcfg.u2_pre_emp = 0x0f; in rk3328_u3phy_tuning()
466 u3phy->apbcfg.u2_pre_emp_sth = 0x41; in rk3328_u3phy_tuning()
469 u3phy->apbcfg.u2_odt_tuning = 0xb5; in rk3328_u3phy_tuning()
474 &u3phy->apbcfg.u2_odt_tuning); in rk3328_u3phy_tuning()
476 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
477 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); in rk3328_u3phy_tuning()
478 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
481 dev_dbg(u3phy->dev, "switch to 25m refclk\n"); in rk3328_u3phy_tuning()
520 dev_err(u3phy->dev, "invalid u3phy port type\n"); in rk3328_u3phy_tuning()