Lines Matching +full:0 +full:- +full:1
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <generic-phy.h>
18 #include <reset-uclass.h>
32 POWER_SUPPLY_TYPE_UNKNOWN = 0,
36 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */
80 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
90 * 0: from phy; 1: from grf
129 * struct rockchip_usb2phy_cfg: usb-phy configuration.
130 * @reg: the address offset of grf for usb-phy config.
169 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; in get_reg_base()
177 tmp = en ? reg->enable : reg->disable; in property_enable()
178 mask = GENMASK(reg->bitend, reg->bitstart); in property_enable()
179 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); in property_enable()
181 return regmap_write(base, reg->offset, val); in property_enable()
188 u32 mask = GENMASK(reg->bitend, reg->bitstart); in property_enabled()
190 regmap_read(base, reg->offset, &orig); in property_enabled()
192 tmp = (orig & mask) >> reg->bitstart; in property_enabled()
194 return tmp == reg->enable; in property_enabled()
218 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); in rockchip_chg_enable_dcd()
219 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); in rockchip_chg_enable_dcd()
227 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); in rockchip_chg_enable_primary_det()
228 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); in rockchip_chg_enable_primary_det()
236 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); in rockchip_chg_enable_secondary_det()
237 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); in rockchip_chg_enable_secondary_det()
245 while (rphy->primary_retries--) { in rockchip_chg_primary_det_retry()
249 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); in rockchip_chg_primary_det_retry()
268 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); in rockchip_chg_get_type()
269 if (ret == -ENODEV) { in rockchip_chg_get_type()
279 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_chg_get_type()
281 /* Check USB-Vbus status first */ in rockchip_chg_get_type()
282 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { in rockchip_chg_get_type()
292 /* Suspend USB-PHY and put the controller in non-driving mode */ in rockchip_chg_get_type()
293 property_enable(base, &port_cfg->phy_sus, true); in rockchip_chg_get_type()
294 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); in rockchip_chg_get_type()
296 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; in rockchip_chg_get_type()
297 rphy->primary_retries = CHG_PRI_MAX_RETRIES; in rockchip_chg_get_type()
299 /* stage 1, start DCD processing stage */ in rockchip_chg_get_type()
302 while (rphy->dcd_retries--) { in rockchip_chg_get_type()
306 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det); in rockchip_chg_get_type()
308 if (is_dcd || !rphy->dcd_retries) { in rockchip_chg_get_type()
320 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det); in rockchip_chg_get_type()
326 if (!rphy->dcd_retries) { in rockchip_chg_get_type()
348 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det); in rockchip_chg_get_type()
357 /* Resume USB-PHY and put the controller in normal mode */ in rockchip_chg_get_type()
358 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); in rockchip_chg_get_type()
359 property_enable(base, &port_cfg->phy_sus, false); in rockchip_chg_get_type()
373 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; in rockchip_u2phy_vbus_detect()
384 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); in otg_phy_init()
385 if (ret == -ENODEV) { in otg_phy_init()
395 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in otg_phy_init()
397 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ in otg_phy_init()
398 if(rphy->phy_cfg->clkout_ctl.disable) in otg_phy_init()
399 property_enable(base, &rphy->phy_cfg->clkout_ctl, true); in otg_phy_init()
401 /* Reset USB-PHY */ in otg_phy_init()
402 property_enable(base, &port_cfg->phy_sus, true); in otg_phy_init()
404 property_enable(base, &port_cfg->phy_sus, false); in otg_phy_init()
412 if (rphy->phy_rst.dev) { in rockchip_usb2phy_reset()
413 ret = reset_assert(&rphy->phy_rst); in rockchip_usb2phy_reset()
414 if (ret < 0) { in rockchip_usb2phy_reset()
421 ret = reset_deassert(&rphy->phy_rst); in rockchip_usb2phy_reset()
422 if (ret < 0) { in rockchip_usb2phy_reset()
430 return 0; in rockchip_usb2phy_reset()
435 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_init()
440 if (phy->id == USB2PHY_PORT_OTG) { in rockchip_usb2phy_init()
441 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_usb2phy_init()
442 } else if (phy->id == USB2PHY_PORT_HOST) { in rockchip_usb2phy_init()
443 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; in rockchip_usb2phy_init()
445 dev_err(phy->dev, "phy id %lu not support", phy->id); in rockchip_usb2phy_init()
446 return -EINVAL; in rockchip_usb2phy_init()
449 property_enable(base, &port_cfg->phy_sus, false); in rockchip_usb2phy_init()
454 return 0; in rockchip_usb2phy_init()
459 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_exit()
464 if (phy->id == USB2PHY_PORT_OTG) { in rockchip_usb2phy_exit()
465 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; in rockchip_usb2phy_exit()
466 } else if (phy->id == USB2PHY_PORT_HOST) { in rockchip_usb2phy_exit()
467 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; in rockchip_usb2phy_exit()
469 dev_err(phy->dev, "phy id %lu not support", phy->id); in rockchip_usb2phy_exit()
470 return -EINVAL; in rockchip_usb2phy_exit()
473 property_enable(base, &port_cfg->phy_sus, true); in rockchip_usb2phy_exit()
475 return 0; in rockchip_usb2phy_exit()
480 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_power_on()
482 struct udevice *vbus = rphy->vbus_supply[phy->id]; in rockchip_usb2phy_power_on()
493 return 0; in rockchip_usb2phy_power_on()
498 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_power_off()
500 struct udevice *vbus = rphy->vbus_supply[phy->id]; in rockchip_usb2phy_power_off()
511 return 0; in rockchip_usb2phy_power_off()
517 const char *dev_name = phy->dev->name; in rockchip_usb2phy_of_xlate()
518 struct udevice *parent = phy->dev->parent; in rockchip_usb2phy_of_xlate()
521 if (!strcasecmp(dev_name, "host-port")) { in rockchip_usb2phy_of_xlate()
522 phy->id = USB2PHY_PORT_HOST; in rockchip_usb2phy_of_xlate()
523 device_get_supply_regulator(phy->dev, "phy-supply", in rockchip_usb2phy_of_xlate()
524 &rphy->vbus_supply[USB2PHY_PORT_HOST]); in rockchip_usb2phy_of_xlate()
525 } else if (!strcasecmp(dev_name, "otg-port")) { in rockchip_usb2phy_of_xlate()
526 phy->id = USB2PHY_PORT_OTG; in rockchip_usb2phy_of_xlate()
527 device_get_supply_regulator(phy->dev, "phy-supply", in rockchip_usb2phy_of_xlate()
528 &rphy->vbus_supply[USB2PHY_PORT_OTG]); in rockchip_usb2phy_of_xlate()
529 if (!rphy->vbus_supply[USB2PHY_PORT_OTG]) in rockchip_usb2phy_of_xlate()
530 device_get_supply_regulator(phy->dev, "vbus-supply", in rockchip_usb2phy_of_xlate()
531 &rphy->vbus_supply[USB2PHY_PORT_OTG]); in rockchip_usb2phy_of_xlate()
534 return -EINVAL; in rockchip_usb2phy_of_xlate()
537 return 0; in rockchip_usb2phy_of_xlate()
549 debug("%s: %s subnode not found", __func__, dev->name); in rockchip_usb2phy_bind()
550 return -ENXIO; in rockchip_usb2phy_bind()
565 return 0; in rockchip_usb2phy_bind()
572 struct udevice *parent = dev->parent; in rockchip_usb2phy_probe()
578 rphy->phy_base = (void __iomem *)dev_read_addr(dev); in rockchip_usb2phy_probe()
579 if (IS_ERR(rphy->phy_base)) { in rockchip_usb2phy_probe()
583 if (!strncmp(parent->name, "root_driver", 11) && in rockchip_usb2phy_probe()
592 rphy->grf_base = syscon_get_regmap(syscon); in rockchip_usb2phy_probe()
594 rphy->grf_base = syscon_get_regmap(parent); in rockchip_usb2phy_probe()
597 if (rphy->grf_base <= 0) { in rockchip_usb2phy_probe()
599 return -EINVAL; in rockchip_usb2phy_probe()
610 rphy->usbgrf_base = syscon_get_regmap(syscon); in rockchip_usb2phy_probe()
611 if (rphy->usbgrf_base <= 0) { in rockchip_usb2phy_probe()
613 return -EINVAL; in rockchip_usb2phy_probe()
616 rphy->usbgrf_base = NULL; in rockchip_usb2phy_probe()
619 if (!strncmp(parent->name, "root_driver", 11)) { in rockchip_usb2phy_probe()
620 ret = dev_read_resource(dev, 0, &res); in rockchip_usb2phy_probe()
628 return -EINVAL; in rockchip_usb2phy_probe()
631 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst); in rockchip_usb2phy_probe()
639 return -EINVAL; in rockchip_usb2phy_probe()
643 index = 0; in rockchip_usb2phy_probe()
646 rphy->phy_cfg = &phy_cfgs[index]; in rockchip_usb2phy_probe()
652 if (!rphy->phy_cfg) { in rockchip_usb2phy_probe()
653 dev_err(dev, "no phy-config can be matched\n"); in rockchip_usb2phy_probe()
654 return -EINVAL; in rockchip_usb2phy_probe()
657 if (rphy->phy_cfg->phy_tuning) in rockchip_usb2phy_probe()
658 rphy->phy_cfg->phy_tuning(rphy); in rockchip_usb2phy_probe()
660 return 0; in rockchip_usb2phy_probe()
666 int ret = 0; in rk322x_usb2phy_tuning()
668 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ in rk322x_usb2phy_tuning()
669 if (rphy->phy_cfg->reg == 0x760) in rk322x_usb2phy_tuning()
670 ret = regmap_write(base, 0x76c, 0x00070004); in rk322x_usb2phy_tuning()
682 /* Enable otg/host port pre-emphasis during non-chirp phase */ in rk3308_usb2phy_tuning()
683 ret = regmap_read(base, 0, &orig); in rk3308_usb2phy_tuning()
686 tmp = orig & ~GENMASK(2, 0); in rk3308_usb2phy_tuning()
687 tmp |= BIT(2) & GENMASK(2, 0); in rk3308_usb2phy_tuning()
688 ret = regmap_write(base, 0, tmp); in rk3308_usb2phy_tuning()
693 ret = regmap_read(base, 0x004, &orig); in rk3308_usb2phy_tuning()
697 tmp |= 0x40 & GENMASK(7, 5); in rk3308_usb2phy_tuning()
698 ret = regmap_write(base, 0x004, tmp); in rk3308_usb2phy_tuning()
702 ret = regmap_read(base, 0x008, &orig); in rk3308_usb2phy_tuning()
705 tmp = orig & ~BIT(0); in rk3308_usb2phy_tuning()
706 tmp |= 0x1 & BIT(0); in rk3308_usb2phy_tuning()
707 ret = regmap_write(base, 0x008, tmp); in rk3308_usb2phy_tuning()
711 /* Enable host port pre-emphasis during non-chirp phase */ in rk3308_usb2phy_tuning()
712 ret = regmap_read(base, 0x400, &orig); in rk3308_usb2phy_tuning()
715 tmp = orig & ~GENMASK(2, 0); in rk3308_usb2phy_tuning()
716 tmp |= BIT(2) & GENMASK(2, 0); in rk3308_usb2phy_tuning()
717 ret = regmap_write(base, 0x400, tmp); in rk3308_usb2phy_tuning()
722 ret = regmap_read(base, 0x404, &orig); in rk3308_usb2phy_tuning()
726 tmp |= 0x40 & GENMASK(7, 5); in rk3308_usb2phy_tuning()
727 ret = regmap_write(base, 0x404, tmp); in rk3308_usb2phy_tuning()
731 ret = regmap_read(base, 0x408, &orig); in rk3308_usb2phy_tuning()
734 tmp = orig & ~BIT(0); in rk3308_usb2phy_tuning()
735 tmp |= 0x1 & BIT(0); in rk3308_usb2phy_tuning()
736 ret = regmap_write(base, 0x408, tmp); in rk3308_usb2phy_tuning()
741 return 0; in rk3308_usb2phy_tuning()
751 /* Enable otg/host port pre-emphasis during non-chirp phase */ in rk3328_usb2phy_tuning()
752 ret = regmap_read(base, 0x8000, &orig); in rk3328_usb2phy_tuning()
755 tmp = orig & ~GENMASK(2, 0); in rk3328_usb2phy_tuning()
756 tmp |= BIT(2) & GENMASK(2, 0); in rk3328_usb2phy_tuning()
757 ret = regmap_write(base, 0x8000, tmp); in rk3328_usb2phy_tuning()
762 ret = regmap_read(base, 0x8004, &orig); in rk3328_usb2phy_tuning()
766 tmp |= 0x40 & GENMASK(7, 5); in rk3328_usb2phy_tuning()
767 ret = regmap_write(base, 0x8004, tmp); in rk3328_usb2phy_tuning()
771 ret = regmap_read(base, 0x8008, &orig); in rk3328_usb2phy_tuning()
774 tmp = orig & ~BIT(0); in rk3328_usb2phy_tuning()
775 tmp |= 0x1 & BIT(0); in rk3328_usb2phy_tuning()
776 ret = regmap_write(base, 0x8008, tmp); in rk3328_usb2phy_tuning()
780 /* Enable host port pre-emphasis during non-chirp phase */ in rk3328_usb2phy_tuning()
781 ret = regmap_read(base, 0x8400, &orig); in rk3328_usb2phy_tuning()
784 tmp = orig & ~GENMASK(2, 0); in rk3328_usb2phy_tuning()
785 tmp |= BIT(2) & GENMASK(2, 0); in rk3328_usb2phy_tuning()
786 ret = regmap_write(base, 0x8400, tmp); in rk3328_usb2phy_tuning()
791 ret = regmap_read(base, 0x8404, &orig); in rk3328_usb2phy_tuning()
795 tmp |= 0x40 & GENMASK(7, 5); in rk3328_usb2phy_tuning()
796 ret = regmap_write(base, 0x8404, tmp); in rk3328_usb2phy_tuning()
800 ret = regmap_read(base, 0x8408, &orig); in rk3328_usb2phy_tuning()
803 tmp = orig & ~BIT(0); in rk3328_usb2phy_tuning()
804 tmp |= 0x1 & BIT(0); in rk3328_usb2phy_tuning()
805 ret = regmap_write(base, 0x8408, tmp); in rk3328_usb2phy_tuning()
810 return 0; in rk3328_usb2phy_tuning()
818 reg = readl(rphy->phy_base + 0x70); in rv1106_usb2phy_tuning()
819 writel(reg | BIT(2), rphy->phy_base + 0x70); in rv1106_usb2phy_tuning()
821 return 0; in rv1106_usb2phy_tuning()
827 int ret = 0; in rk3528_usb2phy_tuning()
829 if (IS_ERR(rphy->phy_base)) { in rk3528_usb2phy_tuning()
830 return PTR_ERR(rphy->phy_base); in rk3528_usb2phy_tuning()
834 reg = readl(rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
835 writel(reg & ~BIT(2), rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
838 reg = readl(rphy->phy_base + 0x0430); in rk3528_usb2phy_tuning()
839 writel(reg & ~BIT(2), rphy->phy_base + 0x0430); in rk3528_usb2phy_tuning()
842 reg = readl(rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
844 reg |= (0x00 << 4); in rk3528_usb2phy_tuning()
845 writel(reg, rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
848 reg = readl(rphy->phy_base + 0x430); in rk3528_usb2phy_tuning()
850 reg |= (0x00 << 4); in rk3528_usb2phy_tuning()
851 writel(reg, rphy->phy_base + 0x430); in rk3528_usb2phy_tuning()
854 reg = readl(rphy->phy_base + 0x94); in rk3528_usb2phy_tuning()
856 reg |= (0x03 << 3); in rk3528_usb2phy_tuning()
857 writel(reg, rphy->phy_base + 0x94); in rk3528_usb2phy_tuning()
860 reg = readl(rphy->phy_base + 0x41c); in rk3528_usb2phy_tuning()
862 reg |= (0x27 << 2); in rk3528_usb2phy_tuning()
863 writel(reg, rphy->phy_base + 0x41c); in rk3528_usb2phy_tuning()
871 int ret = 0; in rk3562_usb2phy_tuning()
873 if (IS_ERR(rphy->phy_base)) { in rk3562_usb2phy_tuning()
874 return PTR_ERR(rphy->phy_base); in rk3562_usb2phy_tuning()
878 reg = readl(rphy->phy_base + 0x30); in rk3562_usb2phy_tuning()
879 writel(reg & ~BIT(2), rphy->phy_base + 0x30); in rk3562_usb2phy_tuning()
881 reg = readl(rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
882 writel(reg & ~BIT(2), rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
884 /* Enable pre-emphasis during non-chirp phase */ in rk3562_usb2phy_tuning()
885 reg = readl(rphy->phy_base); in rk3562_usb2phy_tuning()
886 reg &= ~GENMASK(2, 0); in rk3562_usb2phy_tuning()
887 reg |= 0x04; in rk3562_usb2phy_tuning()
888 writel(reg, rphy->phy_base); in rk3562_usb2phy_tuning()
890 reg = readl(rphy->phy_base + 0x0400); in rk3562_usb2phy_tuning()
891 reg &= ~GENMASK(2, 0); in rk3562_usb2phy_tuning()
892 reg |= 0x04; in rk3562_usb2phy_tuning()
893 writel(reg, rphy->phy_base + 0x0400); in rk3562_usb2phy_tuning()
896 reg = readl(rphy->phy_base + 0x0030); in rk3562_usb2phy_tuning()
898 reg |= (0x05 << 4); in rk3562_usb2phy_tuning()
899 writel(reg, rphy->phy_base + 0x0030); in rk3562_usb2phy_tuning()
901 reg = readl(rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
903 reg |= (0x05 << 4); in rk3562_usb2phy_tuning()
904 writel(reg, rphy->phy_base + 0x0430); in rk3562_usb2phy_tuning()
915 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000); in rk3588_usb2phy_tuning()
925 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900); in rk3588_usb2phy_tuning()
929 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */ in rk3588_usb2phy_tuning()
930 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010); in rk3588_usb2phy_tuning()
934 return 0; in rk3588_usb2phy_tuning()
947 .reg = 0x100,
949 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
952 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
953 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
954 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
955 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
956 .iddig_output = { 0x0100, 10, 10, 0, 1 },
957 .iddig_en = { 0x0100, 9, 9, 0, 1 },
958 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
959 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
960 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
961 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
962 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
963 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
964 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
965 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
966 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
967 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
968 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
969 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
970 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
971 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
974 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 },
975 .ls_det_en = { 0x110, 1, 1, 0, 1 },
976 .ls_det_st = { 0x114, 1, 1, 0, 1 },
977 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
978 .utmi_ls = { 0x120, 17, 16, 0, 1 },
979 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
983 .opmode = { 0x0100, 3, 0, 5, 1 },
984 .cp_det = { 0x0120, 24, 24, 0, 1 },
985 .dcp_det = { 0x0120, 23, 23, 0, 1 },
986 .dp_det = { 0x0120, 25, 25, 0, 1 },
987 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
988 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
989 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
990 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
991 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
992 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1000 .reg = 0x17c,
1002 .clkout_ctl = { 0x017c, 11, 11, 1, 0 },
1005 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1006 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1007 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1008 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1009 .iddig_output = { 0x017c, 10, 10, 0, 1 },
1010 .iddig_en = { 0x017c, 9, 9, 0, 1 },
1011 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1012 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1013 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1014 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1015 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1016 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1017 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1018 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1019 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1020 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1021 .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
1022 .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1025 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1026 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1027 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1028 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1037 .reg = 0x17c,
1039 .clkout_ctl = { 0x0190, 15, 15, 1, 0 },
1042 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1043 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1044 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1045 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1046 .iddig_output = { 0x017c, 10, 10, 0, 1 },
1047 .iddig_en = { 0x017c, 9, 9, 0, 1 },
1048 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1049 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1050 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1051 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1052 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1053 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1054 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1055 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1056 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1057 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1058 .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
1059 .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1062 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1063 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1064 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1065 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1069 .opmode = { 0x017c, 3, 0, 5, 1 },
1070 .cp_det = { 0x02c0, 6, 6, 0, 1 },
1071 .dcp_det = { 0x02c0, 5, 5, 0, 1 },
1072 .dp_det = { 0x02c0, 7, 7, 0, 1 },
1073 .idm_sink_en = { 0x0184, 8, 8, 0, 1 },
1074 .idp_sink_en = { 0x0184, 7, 7, 0, 1 },
1075 .idp_src_en = { 0x0184, 9, 9, 0, 1 },
1076 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 },
1077 .vdm_src_en = { 0x0184, 12, 12, 0, 1 },
1078 .vdp_src_en = { 0x0184, 11, 11, 0, 1 },
1086 .reg = 0x760,
1089 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1092 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 },
1093 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1094 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1095 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1096 .iddig_output = { 0x0760, 10, 10, 0, 1 },
1097 .iddig_en = { 0x0760, 9, 9, 0, 1 },
1098 .idfall_det_en = { 0x0680, 6, 6, 0, 1 },
1099 .idfall_det_st = { 0x0690, 6, 6, 0, 1 },
1100 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 },
1101 .idrise_det_en = { 0x0680, 5, 5, 0, 1 },
1102 .idrise_det_st = { 0x0690, 5, 5, 0, 1 },
1103 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 },
1104 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1105 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1106 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1107 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1108 .utmi_iddig = { 0x0480, 1, 1, 0, 1 },
1109 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1110 .vbus_det_en = { 0x0788, 15, 15, 1, 0 },
1113 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 },
1114 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1115 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1116 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1120 .opmode = { 0x0760, 3, 0, 5, 1 },
1121 .cp_det = { 0x0884, 4, 4, 0, 1 },
1122 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1123 .dp_det = { 0x0884, 5, 5, 0, 1 },
1124 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1125 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1126 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1127 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1128 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1129 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1133 .reg = 0x800,
1135 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1138 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 },
1139 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1140 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1141 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1144 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 },
1145 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1146 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1147 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1156 .reg = 0x100,
1159 .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1162 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1163 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 },
1164 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 },
1165 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 },
1166 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1167 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1168 .idfall_det_en = { 0x3020, 5, 5, 0, 1 },
1169 .idfall_det_st = { 0x3024, 5, 5, 0, 1 },
1170 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 },
1171 .idrise_det_en = { 0x3020, 4, 4, 0, 1 },
1172 .idrise_det_st = { 0x3024, 4, 4, 0, 1 },
1173 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 },
1174 .ls_det_en = { 0x3020, 0, 0, 0, 1 },
1175 .ls_det_st = { 0x3024, 0, 0, 0, 1 },
1176 .ls_det_clr = { 0x3028, 0, 0, 0, 1 },
1177 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1178 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1179 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1180 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1181 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
1184 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 },
1185 .ls_det_en = { 0x3020, 1, 1, 0, 1 },
1186 .ls_det_st = { 0x3024, 1, 1, 0, 1 },
1187 .ls_det_clr = { 0x3028, 1, 1, 0, 1 },
1188 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1189 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1193 .opmode = { 0x0100, 3, 0, 5, 1 },
1194 .cp_det = { 0x0120, 24, 24, 0, 1 },
1195 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1196 .dp_det = { 0x0120, 25, 25, 0, 1 },
1197 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1198 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1199 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1200 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1201 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1202 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1210 .reg = 0x100,
1213 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1216 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1217 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1218 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1219 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1220 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1221 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1222 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1223 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1224 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1225 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1226 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1227 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1228 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1229 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1230 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1231 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1232 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1233 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1234 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1235 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
1238 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 },
1239 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1240 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1241 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1242 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1243 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1247 .opmode = { 0x0100, 3, 0, 5, 1 },
1248 .cp_det = { 0x0120, 24, 24, 0, 1 },
1249 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1250 .dp_det = { 0x0120, 25, 25, 0, 1 },
1251 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1252 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1253 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1254 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1255 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1256 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1264 .reg = 0x700,
1266 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1269 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 },
1270 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1271 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1272 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1273 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1274 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1275 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1276 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 },
1277 .utmi_ls = { 0x04bc, 25, 24, 0, 1 },
1280 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 },
1281 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1282 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1283 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1287 .opmode = { 0x0700, 3, 0, 5, 1 },
1288 .cp_det = { 0x04b8, 30, 30, 0, 1 },
1289 .dcp_det = { 0x04b8, 29, 29, 0, 1 },
1290 .dp_det = { 0x04b8, 31, 31, 0, 1 },
1291 .idm_sink_en = { 0x0718, 8, 8, 0, 1 },
1292 .idp_sink_en = { 0x0718, 7, 7, 0, 1 },
1293 .idp_src_en = { 0x0718, 9, 9, 0, 1 },
1294 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 },
1295 .vdm_src_en = { 0x0718, 12, 12, 0, 1 },
1296 .vdp_src_en = { 0x0718, 11, 11, 0, 1 },
1304 .reg = 0xe450,
1306 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1309 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 },
1310 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1311 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1312 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1313 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1314 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1315 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1316 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1317 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1318 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1319 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 },
1320 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 },
1321 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 },
1322 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1323 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1324 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 },
1325 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 },
1326 .vbus_det_en = { 0x449c, 15, 15, 1, 0 },
1329 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1330 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1331 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1332 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1333 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1334 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1338 .opmode = { 0xe454, 3, 0, 5, 1 },
1339 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1340 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1341 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1342 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1343 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1344 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1345 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1346 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1347 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1351 .reg = 0xe460,
1353 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1356 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 },
1357 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1358 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1359 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1360 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1361 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1362 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1363 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1364 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1365 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1366 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 },
1367 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 },
1368 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 },
1369 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1370 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1371 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 },
1372 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 },
1373 .vbus_det_en = { 0x451c, 15, 15, 1, 0 },
1376 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1377 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1378 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1379 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1380 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1381 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1385 .opmode = { 0xe464, 3, 0, 5, 1 },
1386 .cp_det = { 0xe2ac, 5, 5, 0, 1 },
1387 .dcp_det = { 0xe2ac, 4, 4, 0, 1 },
1388 .dp_det = { 0xe2ac, 3, 3, 0, 1 },
1389 .idm_sink_en = { 0xe460, 8, 8, 0, 1 },
1390 .idp_sink_en = { 0xe460, 7, 7, 0, 1 },
1391 .idp_src_en = { 0xe460, 9, 9, 0, 1 },
1392 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 },
1393 .vdm_src_en = { 0xe460, 12, 12, 0, 1 },
1394 .vdp_src_en = { 0xe460, 11, 11, 0, 1 },
1402 .reg = 0xff3e0000,
1403 .num_ports = 1,
1405 .clkout_ctl = { 0x0058, 4, 4, 1, 0 },
1408 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 },
1409 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 },
1410 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 },
1411 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
1412 .iddig_output = { 0x0050, 10, 10, 0, 1 },
1413 .iddig_en = { 0x0050, 9, 9, 0, 1 },
1414 .idfall_det_en = { 0x0100, 5, 5, 0, 1 },
1415 .idfall_det_st = { 0x0104, 5, 5, 0, 1 },
1416 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
1417 .idrise_det_en = { 0x0100, 4, 4, 0, 1 },
1418 .idrise_det_st = { 0x0104, 4, 4, 0, 1 },
1419 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
1420 .ls_det_en = { 0x0100, 0, 0, 0, 1 },
1421 .ls_det_st = { 0x0104, 0, 0, 0, 1 },
1422 .ls_det_clr = { 0x0108, 0, 0, 0, 1 },
1423 .utmi_avalid = { 0x0060, 10, 10, 0, 1 },
1424 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 },
1425 .utmi_iddig = { 0x0060, 6, 6, 0, 1 },
1426 .utmi_ls = { 0x0060, 5, 4, 0, 1 },
1430 .opmode = { 0x0050, 3, 0, 5, 1 },
1431 .cp_det = { 0x0060, 13, 13, 0, 1 },
1432 .dcp_det = { 0x0060, 12, 12, 0, 1 },
1433 .dp_det = { 0x0060, 14, 14, 0, 1 },
1434 .idm_sink_en = { 0x0058, 8, 8, 0, 1 },
1435 .idp_sink_en = { 0x0058, 7, 7, 0, 1 },
1436 .idp_src_en = { 0x0058, 9, 9, 0, 1 },
1437 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 },
1438 .vdm_src_en = { 0x0058, 12, 12, 0, 1 },
1439 .vdp_src_en = { 0x0058, 11, 11, 0, 1 },
1447 .reg = 0x100,
1449 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1452 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 },
1453 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1454 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1455 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1456 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1457 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1458 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1459 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
1460 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
1463 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 },
1464 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1465 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1466 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1467 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
1468 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
1472 .opmode = { 0x0ffa0100, 3, 0, 5, 1 },
1473 .cp_det = { 0x0804, 1, 1, 0, 1 },
1474 .dcp_det = { 0x0804, 0, 0, 0, 1 },
1475 .dp_det = { 0x0804, 2, 2, 0, 1 },
1476 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 },
1477 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 },
1478 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 },
1479 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 },
1480 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 },
1481 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 },
1489 .reg = 0xffdf0000,
1494 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 },
1495 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 },
1496 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 },
1497 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
1498 .iddig_output = { 0x6004c, 10, 10, 0, 1 },
1499 .iddig_en = { 0x6004c, 9, 9, 0, 1 },
1500 .idfall_det_en = { 0x60074, 5, 5, 0, 1 },
1501 .idfall_det_st = { 0x60078, 5, 5, 0, 1 },
1502 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 },
1503 .idrise_det_en = { 0x60074, 4, 4, 0, 1 },
1504 .idrise_det_st = { 0x60078, 4, 4, 0, 1 },
1505 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 },
1506 .ls_det_en = { 0x60074, 0, 0, 0, 1 },
1507 .ls_det_st = { 0x60078, 0, 0, 0, 1 },
1508 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
1509 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
1510 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
1511 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 },
1512 .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
1515 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 },
1516 .ls_det_en = { 0x60090, 0, 0, 0, 1 },
1517 .ls_det_st = { 0x60094, 0, 0, 0, 1 },
1518 .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
1519 .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
1520 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
1524 .opmode = { 0x6004c, 3, 0, 5, 1 },
1525 .cp_det = { 0x6006c, 19, 19, 0, 1 },
1526 .dcp_det = { 0x6006c, 18, 18, 0, 1 },
1527 .dp_det = { 0x6006c, 20, 20, 0, 1 },
1528 .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
1529 .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
1530 .idp_src_en = { 0x60058, 2, 2, 0, 1 },
1531 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
1532 .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
1533 .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
1540 .reg = 0xff740000,
1543 .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1546 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1547 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1548 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1549 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1550 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1551 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1552 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1553 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1554 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1555 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1556 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1557 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1558 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1559 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1560 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1561 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1562 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1563 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1564 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1567 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
1568 .ls_det_en = { 0x0110, 1, 1, 0, 1 },
1569 .ls_det_st = { 0x0114, 1, 1, 0, 1 },
1570 .ls_det_clr = { 0x0118, 1, 1, 0, 1 },
1571 .utmi_ls = { 0x0120, 17, 16, 0, 1 },
1572 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
1576 .opmode = { 0x0100, 3, 0, 5, 1 },
1577 .cp_det = { 0x0120, 24, 24, 0, 1 },
1578 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1579 .dp_det = { 0x0120, 25, 25, 0, 1 },
1580 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1581 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1582 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1583 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1584 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1585 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1593 .reg = 0xfe8a0000,
1595 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1598 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 },
1599 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
1600 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
1601 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
1602 .iddig_output = { 0x0000, 10, 10, 0, 1 },
1603 .iddig_en = { 0x0000, 9, 9, 0, 1 },
1604 .idfall_det_en = { 0x0080, 5, 5, 0, 1 },
1605 .idfall_det_st = { 0x0084, 5, 5, 0, 1 },
1606 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 },
1607 .idrise_det_en = { 0x0080, 4, 4, 0, 1 },
1608 .idrise_det_st = { 0x0084, 4, 4, 0, 1 },
1609 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 },
1610 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1611 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1612 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1613 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
1614 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
1615 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 },
1616 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
1619 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1620 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1621 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1622 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1623 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1624 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1628 .opmode = { 0x0000, 3, 0, 5, 1 },
1629 .cp_det = { 0x00c0, 24, 24, 0, 1 },
1630 .dcp_det = { 0x00c0, 23, 23, 0, 1 },
1631 .dp_det = { 0x00c0, 25, 25, 0, 1 },
1632 .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
1633 .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
1634 .idp_src_en = { 0x0008, 9, 9, 0, 1 },
1635 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
1636 .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
1637 .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
1641 .reg = 0xfe8b0000,
1643 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1646 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1647 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1648 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1649 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1650 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
1651 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
1654 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1655 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1656 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1657 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1658 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1659 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1668 .reg = 0x0000,
1669 .num_ports = 1,
1671 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1674 .phy_sus = { 0x000c, 11, 11, 0, 1 },
1675 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1676 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1677 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1678 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
1679 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
1680 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 },
1681 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1685 .opmode = { 0x0008, 2, 2, 1, 0 },
1686 .cp_det = { 0x00c0, 0, 0, 0, 1 },
1687 .dcp_det = { 0x00c0, 0, 0, 0, 1 },
1688 .dp_det = { 0x00c0, 1, 1, 1, 0 },
1689 .idm_sink_en = { 0x0008, 5, 5, 1, 0 },
1690 .idp_sink_en = { 0x0008, 5, 5, 0, 1 },
1691 .idp_src_en = { 0x0008, 14, 14, 0, 1 },
1692 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 },
1693 .vdm_src_en = { 0x0008, 7, 6, 0, 3 },
1694 .vdp_src_en = { 0x0008, 7, 6, 0, 3 },
1698 .reg = 0x4000,
1699 .num_ports = 1,
1701 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1705 .phy_sus = { 0x000c, 11, 11, 0, 0 },
1706 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1707 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1708 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1709 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1714 .reg = 0x8000,
1715 .num_ports = 1,
1717 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1720 .phy_sus = { 0x0008, 2, 2, 0, 1 },
1721 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1722 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1723 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1724 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1729 .reg = 0xc000,
1730 .num_ports = 1,
1732 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
1735 .phy_sus = { 0x0008, 2, 2, 0, 1 },
1736 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1737 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1738 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1739 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
1748 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
1751 { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
1754 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
1757 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
1760 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
1763 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
1766 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
1769 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
1772 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
1775 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
1778 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
1781 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
1784 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
1787 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },