Lines Matching refs:data
74 u32 data; in polling_with_timeout() local
78 data = readl(addr) & mask; in polling_with_timeout()
79 } while (data != val && --usec_timout > 0); in polling_with_timeout()
82 return data; in polling_with_timeout()
91 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
139 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_pcie_power_up()
141 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_pcie_power_up()
143 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_pcie_power_up()
145 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
147 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; in comphy_pcie_power_up()
148 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
152 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_pcie_power_up()
154 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
155 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
163 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in comphy_pcie_power_up()
166 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in comphy_pcie_power_up()
169 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in comphy_pcie_power_up()
172 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in comphy_pcie_power_up()
173 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
175 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; in comphy_pcie_power_up()
178 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; in comphy_pcie_power_up()
180 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; in comphy_pcie_power_up()
183 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
186 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; in comphy_pcie_power_up()
193 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; in comphy_pcie_power_up()
194 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; in comphy_pcie_power_up()
196 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; in comphy_pcie_power_up()
199 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
211 data = 0; in comphy_pcie_power_up()
215 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; in comphy_pcie_power_up()
222 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; in comphy_pcie_power_up()
225 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; in comphy_pcie_power_up()
229 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_pcie_power_up()
233 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_pcie_power_up()
236 data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; in comphy_pcie_power_up()
237 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_pcie_power_up()
241 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_pcie_power_up()
245 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_pcie_power_up()
249 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_pcie_power_up()
250 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_pcie_power_up()
255 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; in comphy_pcie_power_up()
256 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in comphy_pcie_power_up()
271 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; in comphy_pcie_power_up()
274 data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; in comphy_pcie_power_up()
277 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; in comphy_pcie_power_up()
278 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in comphy_pcie_power_up()
282 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; in comphy_pcie_power_up()
285 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; in comphy_pcie_power_up()
286 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in comphy_pcie_power_up()
290 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; in comphy_pcie_power_up()
293 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; in comphy_pcie_power_up()
296 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; in comphy_pcie_power_up()
297 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
301 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; in comphy_pcie_power_up()
304 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; in comphy_pcie_power_up()
305 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_pcie_power_up()
310 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; in comphy_pcie_power_up()
313 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; in comphy_pcie_power_up()
316 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; in comphy_pcie_power_up()
317 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in comphy_pcie_power_up()
321 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; in comphy_pcie_power_up()
324 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; in comphy_pcie_power_up()
327 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; in comphy_pcie_power_up()
330 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; in comphy_pcie_power_up()
331 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_pcie_power_up()
335 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in comphy_pcie_power_up()
336 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_pcie_power_up()
340 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; in comphy_pcie_power_up()
341 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in comphy_pcie_power_up()
346 data = 0; in comphy_pcie_power_up()
347 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
351 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_pcie_power_up()
352 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_pcie_power_up()
356 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; in comphy_pcie_power_up()
357 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_pcie_power_up()
361 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_pcie_power_up()
362 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_pcie_power_up()
366 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; in comphy_pcie_power_up()
369 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; in comphy_pcie_power_up()
372 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in comphy_pcie_power_up()
373 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_pcie_power_up()
377 data = 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_pcie_power_up()
378 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_pcie_power_up()
384 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in comphy_pcie_power_up()
387 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_pcie_power_up()
388 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_pcie_power_up()
392 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in comphy_pcie_power_up()
393 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_pcie_power_up()
397 data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; in comphy_pcie_power_up()
399 data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; in comphy_pcie_power_up()
401 data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; in comphy_pcie_power_up()
402 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in comphy_pcie_power_up()
404 data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; in comphy_pcie_power_up()
405 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in comphy_pcie_power_up()
409 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; in comphy_pcie_power_up()
411 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; in comphy_pcie_power_up()
413 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; in comphy_pcie_power_up()
414 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_pcie_power_up()
418 data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; in comphy_pcie_power_up()
419 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in comphy_pcie_power_up()
423 data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; in comphy_pcie_power_up()
424 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_pcie_power_up()
428 data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_pcie_power_up()
429 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_pcie_power_up()
433 data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; in comphy_pcie_power_up()
434 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in comphy_pcie_power_up()
438 data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; in comphy_pcie_power_up()
440 data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; in comphy_pcie_power_up()
442 data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; in comphy_pcie_power_up()
443 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in comphy_pcie_power_up()
448 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; in comphy_pcie_power_up()
449 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); in comphy_pcie_power_up()
505 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in comphy_pcie_power_up()
506 mask = data; in comphy_pcie_power_up()
507 data = polling_with_timeout(addr, data, mask, 15000); in comphy_pcie_power_up()
508 if (data != 0) { in comphy_pcie_power_up()
511 data); in comphy_pcie_power_up()
525 u32 mask, data, ret = 1; in comphy_usb3_power_up() local
534 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_usb3_power_up()
536 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_usb3_power_up()
538 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_usb3_power_up()
540 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
542 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; in comphy_usb3_power_up()
543 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
547 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_usb3_power_up()
549 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
550 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
559 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in comphy_usb3_power_up()
562 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in comphy_usb3_power_up()
565 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in comphy_usb3_power_up()
568 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in comphy_usb3_power_up()
569 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_usb3_power_up()
580 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_usb3_power_up()
583 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_usb3_power_up()
584 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_usb3_power_up()
610 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; in comphy_usb3_power_up()
613 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; in comphy_usb3_power_up()
616 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; in comphy_usb3_power_up()
617 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_usb3_power_up()
630 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in comphy_usb3_power_up()
631 mask = data; in comphy_usb3_power_up()
632 data = polling_with_timeout(addr, data, mask, 15000); in comphy_usb3_power_up()
633 if (data != 0) { in comphy_usb3_power_up()
635 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); in comphy_usb3_power_up()
647 u32 mask, data, i, ret = 1; in comphy_sata_power_up() local
692 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; in comphy_sata_power_up()
695 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; in comphy_sata_power_up()
698 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; in comphy_sata_power_up()
701 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; in comphy_sata_power_up()
702 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
707 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sata_power_up()
709 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sata_power_up()
711 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_sata_power_up()
713 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_sata_power_up()
714 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sata_power_up()
723 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sata_power_up()
725 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sata_power_up()
726 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sata_power_up()
739 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sata_power_up()
742 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sata_power_up()
743 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sata_power_up()
756 data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
758 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sata_power_up()
760 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
762 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
764 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
765 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sata_power_up()
768 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in comphy_sata_power_up()
770 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in comphy_sata_power_up()
772 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in comphy_sata_power_up()
774 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; in comphy_sata_power_up()
776 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_sata_power_up()
777 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sata_power_up()
781 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
783 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; in comphy_sata_power_up()
785 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
787 data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
789 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
790 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_sata_power_up()
794 data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
796 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; in comphy_sata_power_up()
798 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
800 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
802 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; in comphy_sata_power_up()
804 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
806 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in comphy_sata_power_up()
807 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_sata_power_up()
811 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; in comphy_sata_power_up()
813 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; in comphy_sata_power_up()
815 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sata_power_up()
817 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; in comphy_sata_power_up()
819 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; in comphy_sata_power_up()
821 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; in comphy_sata_power_up()
823 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; in comphy_sata_power_up()
824 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sata_power_up()
828 data = 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_sata_power_up()
829 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
831 data = 0x0 << HPIPE_SMAPLER_OFFSET; in comphy_sata_power_up()
832 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
836 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_sata_power_up()
837 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sata_power_up()
841 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_sata_power_up()
842 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sata_power_up()
846 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_sata_power_up()
848 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_sata_power_up()
849 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sata_power_up()
853 data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; in comphy_sata_power_up()
855 data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; in comphy_sata_power_up()
857 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; in comphy_sata_power_up()
859 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in comphy_sata_power_up()
861 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_sata_power_up()
862 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_sata_power_up()
866 data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; in comphy_sata_power_up()
867 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_sata_power_up()
871 data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; in comphy_sata_power_up()
873 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; in comphy_sata_power_up()
874 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
876 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; in comphy_sata_power_up()
877 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
879 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; in comphy_sata_power_up()
880 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
884 data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; in comphy_sata_power_up()
886 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
888 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sata_power_up()
890 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
891 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sata_power_up()
895 data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; in comphy_sata_power_up()
897 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
899 data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; in comphy_sata_power_up()
901 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
902 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in comphy_sata_power_up()
906 data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; in comphy_sata_power_up()
908 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
910 data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; in comphy_sata_power_up()
912 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
914 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; in comphy_sata_power_up()
916 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; in comphy_sata_power_up()
917 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in comphy_sata_power_up()
921 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; in comphy_sata_power_up()
922 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sata_power_up()
949 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; in comphy_sata_power_up()
952 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; in comphy_sata_power_up()
955 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; in comphy_sata_power_up()
958 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; in comphy_sata_power_up()
959 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
972 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & in comphy_sata_power_up()
974 mask = data; in comphy_sata_power_up()
975 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sata_power_up()
976 if (data != 0) { in comphy_sata_power_up()
978 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); in comphy_sata_power_up()
980 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), in comphy_sata_power_up()
981 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); in comphy_sata_power_up()
993 u32 mask, data, ret = 1; in comphy_sgmii_power_up() local
1003 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sgmii_power_up()
1005 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sgmii_power_up()
1006 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sgmii_power_up()
1010 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sgmii_power_up()
1014 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sgmii_power_up()
1015 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sgmii_power_up()
1018 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sgmii_power_up()
1019 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sgmii_power_up()
1022 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sgmii_power_up()
1024 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sgmii_power_up()
1026 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_sgmii_power_up()
1027 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1031 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1033 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sgmii_power_up()
1035 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1036 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1040 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1042 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sgmii_power_up()
1043 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1053 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_sgmii_power_up()
1054 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sgmii_power_up()
1057 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sgmii_power_up()
1059 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sgmii_power_up()
1060 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sgmii_power_up()
1063 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in comphy_sgmii_power_up()
1064 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sgmii_power_up()
1067 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_sgmii_power_up()
1069 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_sgmii_power_up()
1070 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sgmii_power_up()
1073 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sgmii_power_up()
1074 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sgmii_power_up()
1086 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sgmii_power_up()
1088 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sgmii_power_up()
1090 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sgmii_power_up()
1091 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1095 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_sgmii_power_up()
1097 mask = data; in comphy_sgmii_power_up()
1098 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sgmii_power_up()
1099 if (data != 0) { in comphy_sgmii_power_up()
1101 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1103 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_sgmii_power_up()
1104 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_sgmii_power_up()
1110 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sgmii_power_up()
1111 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1115 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_sgmii_power_up()
1116 mask = data; in comphy_sgmii_power_up()
1117 data = polling_with_timeout(addr, data, mask, 100); in comphy_sgmii_power_up()
1118 if (data != 0) { in comphy_sgmii_power_up()
1119 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1127 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sgmii_power_up()
1129 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1130 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1139 u32 mask, data, ret = 1; in comphy_sfi_power_up() local
1149 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sfi_power_up()
1151 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sfi_power_up()
1152 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sfi_power_up()
1156 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sfi_power_up()
1158 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sfi_power_up()
1160 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sfi_power_up()
1162 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sfi_power_up()
1164 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sfi_power_up()
1166 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_sfi_power_up()
1167 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1171 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sfi_power_up()
1173 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sfi_power_up()
1175 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sfi_power_up()
1176 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1179 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sfi_power_up()
1181 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sfi_power_up()
1182 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1192 data = (speed == PHY_SPEED_5_15625G) ? in comphy_sfi_power_up()
1196 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_sfi_power_up()
1197 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sfi_power_up()
1200 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sfi_power_up()
1202 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sfi_power_up()
1203 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sfi_power_up()
1206 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in comphy_sfi_power_up()
1207 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sfi_power_up()
1210 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_sfi_power_up()
1212 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_sfi_power_up()
1213 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sfi_power_up()
1216 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sfi_power_up()
1217 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sfi_power_up()
1222 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1224 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1226 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1228 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1231 data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1233 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in comphy_sfi_power_up()
1239 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; in comphy_sfi_power_up()
1240 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sfi_power_up()
1243 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_sfi_power_up()
1244 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sfi_power_up()
1248 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sfi_power_up()
1251 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; in comphy_sfi_power_up()
1253 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sfi_power_up()
1255 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sfi_power_up()
1258 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; in comphy_sfi_power_up()
1260 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; in comphy_sfi_power_up()
1261 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in comphy_sfi_power_up()
1264 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; in comphy_sfi_power_up()
1266 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; in comphy_sfi_power_up()
1267 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in comphy_sfi_power_up()
1270 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in comphy_sfi_power_up()
1272 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; in comphy_sfi_power_up()
1273 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in comphy_sfi_power_up()
1276 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in comphy_sfi_power_up()
1277 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in comphy_sfi_power_up()
1280 data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in comphy_sfi_power_up()
1283 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sfi_power_up()
1285 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sfi_power_up()
1288 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sfi_power_up()
1290 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sfi_power_up()
1292 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; in comphy_sfi_power_up()
1294 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; in comphy_sfi_power_up()
1296 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in comphy_sfi_power_up()
1298 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sfi_power_up()
1302 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_sfi_power_up()
1304 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_sfi_power_up()
1305 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sfi_power_up()
1309 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in comphy_sfi_power_up()
1310 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_sfi_power_up()
1313 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; in comphy_sfi_power_up()
1317 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in comphy_sfi_power_up()
1319 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in comphy_sfi_power_up()
1321 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in comphy_sfi_power_up()
1323 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sfi_power_up()
1327 data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; in comphy_sfi_power_up()
1328 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_sfi_power_up()
1332 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in comphy_sfi_power_up()
1333 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1337 data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; in comphy_sfi_power_up()
1338 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in comphy_sfi_power_up()
1342 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in comphy_sfi_power_up()
1343 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_sfi_power_up()
1347 data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; in comphy_sfi_power_up()
1349 data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; in comphy_sfi_power_up()
1350 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_sfi_power_up()
1354 data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; in comphy_sfi_power_up()
1355 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1359 data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; in comphy_sfi_power_up()
1360 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in comphy_sfi_power_up()
1364 data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; in comphy_sfi_power_up()
1365 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in comphy_sfi_power_up()
1369 data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; in comphy_sfi_power_up()
1371 data |= 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_sfi_power_up()
1372 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1374 data = 0x0 << HPIPE_SMAPLER_OFFSET; in comphy_sfi_power_up()
1375 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1379 data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_sfi_power_up()
1380 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sfi_power_up()
1385 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sfi_power_up()
1387 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sfi_power_up()
1389 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sfi_power_up()
1390 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1395 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_sfi_power_up()
1397 mask = data; in comphy_sfi_power_up()
1398 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sfi_power_up()
1399 if (data != 0) { in comphy_sfi_power_up()
1400 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1402 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_sfi_power_up()
1403 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_sfi_power_up()
1409 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sfi_power_up()
1410 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1415 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_sfi_power_up()
1416 mask = data; in comphy_sfi_power_up()
1417 data = polling_with_timeout(addr, data, mask, 100); in comphy_sfi_power_up()
1418 if (data != 0) { in comphy_sfi_power_up()
1420 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1428 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sfi_power_up()
1430 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sfi_power_up()
1431 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1440 u32 mask, data, ret = 1; in comphy_rxauii_power_up() local
1450 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_rxauii_power_up()
1452 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_rxauii_power_up()
1453 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_rxauii_power_up()
1468 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_rxauii_power_up()
1470 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_rxauii_power_up()
1472 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_rxauii_power_up()
1474 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_rxauii_power_up()
1476 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_rxauii_power_up()
1478 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_rxauii_power_up()
1480 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; in comphy_rxauii_power_up()
1481 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1485 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1487 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_rxauii_power_up()
1489 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1490 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1493 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1495 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_rxauii_power_up()
1496 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1509 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_rxauii_power_up()
1511 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_rxauii_power_up()
1512 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_rxauii_power_up()
1518 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_rxauii_power_up()
1520 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_rxauii_power_up()
1521 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_rxauii_power_up()
1542 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_rxauii_power_up()
1544 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_rxauii_power_up()
1546 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in comphy_rxauii_power_up()
1547 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_rxauii_power_up()
1550 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_rxauii_power_up()
1552 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_rxauii_power_up()
1553 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_rxauii_power_up()
1557 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in comphy_rxauii_power_up()
1558 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_rxauii_power_up()
1563 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_rxauii_power_up()
1565 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_rxauii_power_up()
1567 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_rxauii_power_up()
1568 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1573 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_rxauii_power_up()
1575 mask = data; in comphy_rxauii_power_up()
1576 data = polling_with_timeout(addr, data, mask, 15000); in comphy_rxauii_power_up()
1577 if (data != 0) { in comphy_rxauii_power_up()
1579 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_rxauii_power_up()
1581 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_rxauii_power_up()
1582 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_rxauii_power_up()
1593 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_rxauii_power_up()
1594 mask = data; in comphy_rxauii_power_up()
1595 data = polling_with_timeout(addr, data, mask, 100); in comphy_rxauii_power_up()
1596 if (data != 0) { in comphy_rxauii_power_up()
1598 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_rxauii_power_up()
1606 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_rxauii_power_up()
1608 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1609 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1620 u32 mask, data; in comphy_utmi_power_down() local
1638 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; in comphy_utmi_power_down()
1641 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; in comphy_utmi_power_down()
1642 reg_set(usb_cfg_addr, data, mask); in comphy_utmi_power_down()
1647 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; in comphy_utmi_power_down()
1650 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; in comphy_utmi_power_down()
1651 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); in comphy_utmi_power_down()
1665 u32 mask, data; in comphy_utmi_phy_config() local
1671 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; in comphy_utmi_phy_config()
1674 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; in comphy_utmi_phy_config()
1677 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; in comphy_utmi_phy_config()
1678 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1687 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; in comphy_utmi_phy_config()
1690 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; in comphy_utmi_phy_config()
1691 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1695 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; in comphy_utmi_phy_config()
1698 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; in comphy_utmi_phy_config()
1699 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); in comphy_utmi_phy_config()
1703 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; in comphy_utmi_phy_config()
1706 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; in comphy_utmi_phy_config()
1707 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); in comphy_utmi_phy_config()
1711 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; in comphy_utmi_phy_config()
1714 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; in comphy_utmi_phy_config()
1715 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1725 u32 data, mask, ret = 1; in comphy_utmi_power_up() local
1741 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; in comphy_utmi_power_up()
1742 mask = data; in comphy_utmi_power_up()
1743 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1744 if (data != 0) { in comphy_utmi_power_up()
1746 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1750 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; in comphy_utmi_power_up()
1751 mask = data; in comphy_utmi_power_up()
1752 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1753 if (data != 0) { in comphy_utmi_power_up()
1755 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1760 data = UTMI_PLL_CTRL_PLL_RDY_MASK; in comphy_utmi_power_up()
1761 mask = data; in comphy_utmi_power_up()
1762 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1763 if (data != 0) { in comphy_utmi_power_up()
1765 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()