Lines Matching full:mask
72 u32 mask, unsigned long usec_timout) in polling_with_timeout() argument
78 data = readl(addr) & mask; in polling_with_timeout()
91 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
138 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_pcie_power_up()
140 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_pcie_power_up()
142 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_pcie_power_up()
144 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_pcie_power_up()
146 mask |= COMMON_PHY_PHY_MODE_MASK; in comphy_pcie_power_up()
148 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
151 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_pcie_power_up()
153 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_pcie_power_up()
155 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
162 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in comphy_pcie_power_up()
165 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in comphy_pcie_power_up()
168 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in comphy_pcie_power_up()
171 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in comphy_pcie_power_up()
173 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
176 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; in comphy_pcie_power_up()
179 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; in comphy_pcie_power_up()
181 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; in comphy_pcie_power_up()
183 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
187 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; in comphy_pcie_power_up()
189 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; in comphy_pcie_power_up()
190 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; in comphy_pcie_power_up()
191 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; in comphy_pcie_power_up()
199 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
210 mask = 0; in comphy_pcie_power_up()
214 mask |= HPIPE_MISC_CLK100M_125M_MASK; in comphy_pcie_power_up()
221 mask |= HPIPE_MISC_TXDCLK_2X_MASK; in comphy_pcie_power_up()
224 mask |= HPIPE_MISC_CLK500_EN_MASK; in comphy_pcie_power_up()
228 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in comphy_pcie_power_up()
232 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in comphy_pcie_power_up()
235 mask |= HPIPE_MISC_ICP_FORCE_MASK; in comphy_pcie_power_up()
237 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_pcie_power_up()
240 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_pcie_power_up()
244 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_pcie_power_up()
248 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_pcie_power_up()
250 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_pcie_power_up()
254 mask = HPIPE_LANE_ALIGN_OFF_MASK; in comphy_pcie_power_up()
256 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in comphy_pcie_power_up()
270 mask = HPIPE_INTERFACE_GEN_MAX_MASK; in comphy_pcie_power_up()
273 mask = HPIPE_INTERFACE_DET_BYPASS_MASK; in comphy_pcie_power_up()
276 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; in comphy_pcie_power_up()
278 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in comphy_pcie_power_up()
281 mask = HPIPE_PCIE_IDLE_SYNC_MASK; in comphy_pcie_power_up()
284 mask |= HPIPE_PCIE_SEL_BITS_MASK; in comphy_pcie_power_up()
286 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in comphy_pcie_power_up()
289 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; in comphy_pcie_power_up()
292 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; in comphy_pcie_power_up()
295 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; in comphy_pcie_power_up()
297 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
300 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; in comphy_pcie_power_up()
303 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; in comphy_pcie_power_up()
305 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_pcie_power_up()
309 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; in comphy_pcie_power_up()
312 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; in comphy_pcie_power_up()
315 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; in comphy_pcie_power_up()
317 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in comphy_pcie_power_up()
320 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; in comphy_pcie_power_up()
323 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; in comphy_pcie_power_up()
326 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; in comphy_pcie_power_up()
329 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; in comphy_pcie_power_up()
331 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_pcie_power_up()
334 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in comphy_pcie_power_up()
336 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_pcie_power_up()
339 mask = HPIPE_TRX_TRAIN_TIMER_MASK; in comphy_pcie_power_up()
341 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in comphy_pcie_power_up()
344 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK in comphy_pcie_power_up()
347 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
350 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_pcie_power_up()
352 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_pcie_power_up()
355 mask = HPIPE_G3_DFE_RES_MASK; in comphy_pcie_power_up()
357 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_pcie_power_up()
360 mask = HPIPE_DFE_RES_FORCE_MASK; in comphy_pcie_power_up()
362 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_pcie_power_up()
365 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in comphy_pcie_power_up()
368 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in comphy_pcie_power_up()
371 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in comphy_pcie_power_up()
373 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_pcie_power_up()
376 mask = HPIPE_SMAPLER_MASK; in comphy_pcie_power_up()
378 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_pcie_power_up()
380 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); in comphy_pcie_power_up()
383 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in comphy_pcie_power_up()
386 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in comphy_pcie_power_up()
388 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_pcie_power_up()
391 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in comphy_pcie_power_up()
393 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_pcie_power_up()
396 mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; in comphy_pcie_power_up()
398 mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; in comphy_pcie_power_up()
400 mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; in comphy_pcie_power_up()
402 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in comphy_pcie_power_up()
403 mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; in comphy_pcie_power_up()
405 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in comphy_pcie_power_up()
408 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in comphy_pcie_power_up()
410 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; in comphy_pcie_power_up()
412 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in comphy_pcie_power_up()
414 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_pcie_power_up()
417 mask = HPIPE_G2_DFE_RES_MASK; in comphy_pcie_power_up()
419 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in comphy_pcie_power_up()
422 mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; in comphy_pcie_power_up()
424 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_pcie_power_up()
427 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in comphy_pcie_power_up()
429 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_pcie_power_up()
432 mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; in comphy_pcie_power_up()
434 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in comphy_pcie_power_up()
437 mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; in comphy_pcie_power_up()
439 mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; in comphy_pcie_power_up()
441 mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; in comphy_pcie_power_up()
443 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in comphy_pcie_power_up()
447 mask = HPIPE_CFG_PHY_RC_EP_MASK; in comphy_pcie_power_up()
449 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); in comphy_pcie_power_up()
506 mask = data; in comphy_pcie_power_up()
507 data = polling_with_timeout(addr, data, mask, 15000); in comphy_pcie_power_up()
525 u32 mask, data, ret = 1; in comphy_usb3_power_up() local
533 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_usb3_power_up()
535 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_usb3_power_up()
537 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_usb3_power_up()
539 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_usb3_power_up()
541 mask |= COMMON_PHY_PHY_MODE_MASK; in comphy_usb3_power_up()
543 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
546 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_usb3_power_up()
548 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_usb3_power_up()
550 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
558 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in comphy_usb3_power_up()
561 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in comphy_usb3_power_up()
564 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in comphy_usb3_power_up()
567 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in comphy_usb3_power_up()
569 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_usb3_power_up()
579 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_usb3_power_up()
582 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_usb3_power_up()
584 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_usb3_power_up()
609 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; in comphy_usb3_power_up()
612 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; in comphy_usb3_power_up()
615 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; in comphy_usb3_power_up()
617 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_usb3_power_up()
631 mask = data; in comphy_usb3_power_up()
632 data = polling_with_timeout(addr, data, mask, 15000); in comphy_usb3_power_up()
647 u32 mask, data, i, ret = 1; in comphy_sata_power_up() local
691 mask = SATA3_CTRL_SATA0_PD_MASK; in comphy_sata_power_up()
694 mask |= SATA3_CTRL_SATA1_PD_MASK; in comphy_sata_power_up()
697 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; in comphy_sata_power_up()
700 mask |= SATA3_CTRL_SATA_SSU_MASK; in comphy_sata_power_up()
702 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
706 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_sata_power_up()
708 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_sata_power_up()
710 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_sata_power_up()
712 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_sata_power_up()
714 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sata_power_up()
722 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sata_power_up()
724 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sata_power_up()
726 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sata_power_up()
738 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_sata_power_up()
741 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_sata_power_up()
743 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sata_power_up()
755 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_sata_power_up()
757 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_sata_power_up()
759 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in comphy_sata_power_up()
761 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in comphy_sata_power_up()
763 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in comphy_sata_power_up()
765 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sata_power_up()
767 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in comphy_sata_power_up()
769 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in comphy_sata_power_up()
771 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in comphy_sata_power_up()
773 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; in comphy_sata_power_up()
775 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; in comphy_sata_power_up()
777 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sata_power_up()
780 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in comphy_sata_power_up()
782 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; in comphy_sata_power_up()
784 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in comphy_sata_power_up()
786 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; in comphy_sata_power_up()
788 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; in comphy_sata_power_up()
790 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_sata_power_up()
793 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in comphy_sata_power_up()
795 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in comphy_sata_power_up()
797 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; in comphy_sata_power_up()
799 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; in comphy_sata_power_up()
801 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; in comphy_sata_power_up()
803 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; in comphy_sata_power_up()
805 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in comphy_sata_power_up()
807 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_sata_power_up()
810 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; in comphy_sata_power_up()
812 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; in comphy_sata_power_up()
814 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_sata_power_up()
816 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; in comphy_sata_power_up()
818 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; in comphy_sata_power_up()
820 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; in comphy_sata_power_up()
822 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; in comphy_sata_power_up()
824 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sata_power_up()
827 mask = HPIPE_SMAPLER_MASK; in comphy_sata_power_up()
829 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
830 mask = HPIPE_SMAPLER_MASK; in comphy_sata_power_up()
832 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
835 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in comphy_sata_power_up()
837 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sata_power_up()
840 mask = HPIPE_DFE_RES_FORCE_MASK; in comphy_sata_power_up()
842 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sata_power_up()
845 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in comphy_sata_power_up()
847 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in comphy_sata_power_up()
849 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sata_power_up()
852 mask = HPIPE_G3_FFE_CAP_SEL_MASK; in comphy_sata_power_up()
854 mask |= HPIPE_G3_FFE_RES_SEL_MASK; in comphy_sata_power_up()
856 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; in comphy_sata_power_up()
858 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in comphy_sata_power_up()
860 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in comphy_sata_power_up()
862 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_sata_power_up()
865 mask = HPIPE_G3_DFE_RES_MASK; in comphy_sata_power_up()
867 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_sata_power_up()
870 mask = HPIPE_OS_PH_OFFSET_MASK; in comphy_sata_power_up()
872 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; in comphy_sata_power_up()
874 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
875 mask = HPIPE_OS_PH_VALID_MASK; in comphy_sata_power_up()
877 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
878 mask = HPIPE_OS_PH_VALID_MASK; in comphy_sata_power_up()
880 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
883 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in comphy_sata_power_up()
885 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; in comphy_sata_power_up()
887 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in comphy_sata_power_up()
889 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; in comphy_sata_power_up()
891 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sata_power_up()
894 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; in comphy_sata_power_up()
896 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; in comphy_sata_power_up()
898 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; in comphy_sata_power_up()
900 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; in comphy_sata_power_up()
902 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in comphy_sata_power_up()
905 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; in comphy_sata_power_up()
907 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; in comphy_sata_power_up()
909 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; in comphy_sata_power_up()
911 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; in comphy_sata_power_up()
913 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; in comphy_sata_power_up()
915 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; in comphy_sata_power_up()
917 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in comphy_sata_power_up()
920 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; in comphy_sata_power_up()
922 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sata_power_up()
948 mask = SATA3_CTRL_SATA0_PD_MASK; in comphy_sata_power_up()
951 mask |= SATA3_CTRL_SATA1_PD_MASK; in comphy_sata_power_up()
954 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; in comphy_sata_power_up()
957 mask |= SATA3_CTRL_SATA_SSU_MASK; in comphy_sata_power_up()
959 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
974 mask = data; in comphy_sata_power_up()
975 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sata_power_up()
993 u32 mask, data, ret = 1; in comphy_sgmii_power_up() local
1002 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_sgmii_power_up()
1004 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_sgmii_power_up()
1006 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sgmii_power_up()
1009 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sgmii_power_up()
1011 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in comphy_sgmii_power_up()
1012 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in comphy_sgmii_power_up()
1021 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sgmii_power_up()
1023 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sgmii_power_up()
1025 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in comphy_sgmii_power_up()
1027 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1030 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sgmii_power_up()
1032 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sgmii_power_up()
1034 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sgmii_power_up()
1036 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1039 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sgmii_power_up()
1041 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sgmii_power_up()
1043 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1052 mask = HPIPE_MISC_REFCLK_SEL_MASK; in comphy_sgmii_power_up()
1054 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sgmii_power_up()
1056 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_sgmii_power_up()
1058 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_sgmii_power_up()
1060 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sgmii_power_up()
1062 mask = HPIPE_LOOPBACK_SEL_MASK; in comphy_sgmii_power_up()
1064 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sgmii_power_up()
1066 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in comphy_sgmii_power_up()
1068 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in comphy_sgmii_power_up()
1070 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sgmii_power_up()
1072 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_sgmii_power_up()
1074 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sgmii_power_up()
1085 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sgmii_power_up()
1087 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sgmii_power_up()
1089 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sgmii_power_up()
1091 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1097 mask = data; in comphy_sgmii_power_up()
1098 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sgmii_power_up()
1109 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sgmii_power_up()
1111 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1116 mask = data; in comphy_sgmii_power_up()
1117 data = polling_with_timeout(addr, data, mask, 100); in comphy_sgmii_power_up()
1126 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sgmii_power_up()
1128 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sgmii_power_up()
1130 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1139 u32 mask, data, ret = 1; in comphy_sfi_power_up() local
1148 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_sfi_power_up()
1150 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_sfi_power_up()
1152 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sfi_power_up()
1155 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sfi_power_up()
1157 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in comphy_sfi_power_up()
1159 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in comphy_sfi_power_up()
1161 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sfi_power_up()
1163 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sfi_power_up()
1165 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in comphy_sfi_power_up()
1167 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1170 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sfi_power_up()
1172 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sfi_power_up()
1174 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sfi_power_up()
1176 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1178 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sfi_power_up()
1180 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sfi_power_up()
1182 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1191 mask = HPIPE_MISC_ICP_FORCE_MASK; in comphy_sfi_power_up()
1195 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in comphy_sfi_power_up()
1197 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sfi_power_up()
1199 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_sfi_power_up()
1201 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_sfi_power_up()
1203 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sfi_power_up()
1205 mask = HPIPE_LOOPBACK_SEL_MASK; in comphy_sfi_power_up()
1207 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sfi_power_up()
1209 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in comphy_sfi_power_up()
1211 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in comphy_sfi_power_up()
1213 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sfi_power_up()
1215 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_sfi_power_up()
1217 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sfi_power_up()
1221 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; in comphy_sfi_power_up()
1223 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; in comphy_sfi_power_up()
1225 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; in comphy_sfi_power_up()
1227 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; in comphy_sfi_power_up()
1230 mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; in comphy_sfi_power_up()
1233 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in comphy_sfi_power_up()
1238 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; in comphy_sfi_power_up()
1240 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sfi_power_up()
1242 mask = HPIPE_DFE_RES_FORCE_MASK; in comphy_sfi_power_up()
1244 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sfi_power_up()
1247 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in comphy_sfi_power_up()
1250 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in comphy_sfi_power_up()
1252 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in comphy_sfi_power_up()
1255 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sfi_power_up()
1257 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; in comphy_sfi_power_up()
1259 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; in comphy_sfi_power_up()
1261 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in comphy_sfi_power_up()
1263 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; in comphy_sfi_power_up()
1265 mask |= HPIPE_TX_REG1_SLC_EN_MASK; in comphy_sfi_power_up()
1267 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in comphy_sfi_power_up()
1269 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; in comphy_sfi_power_up()
1271 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; in comphy_sfi_power_up()
1273 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in comphy_sfi_power_up()
1275 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; in comphy_sfi_power_up()
1277 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in comphy_sfi_power_up()
1279 mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in comphy_sfi_power_up()
1282 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_sfi_power_up()
1284 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_sfi_power_up()
1287 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_sfi_power_up()
1289 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_sfi_power_up()
1291 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in comphy_sfi_power_up()
1293 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in comphy_sfi_power_up()
1295 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in comphy_sfi_power_up()
1298 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sfi_power_up()
1301 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in comphy_sfi_power_up()
1303 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in comphy_sfi_power_up()
1305 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sfi_power_up()
1308 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in comphy_sfi_power_up()
1310 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_sfi_power_up()
1312 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; in comphy_sfi_power_up()
1316 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in comphy_sfi_power_up()
1318 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in comphy_sfi_power_up()
1320 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in comphy_sfi_power_up()
1323 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sfi_power_up()
1326 mask = HPIPE_RX_TRAIN_TIMER_MASK; in comphy_sfi_power_up()
1328 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_sfi_power_up()
1331 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in comphy_sfi_power_up()
1333 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1336 mask = HPIPE_TX_PRESET_INDEX_MASK; in comphy_sfi_power_up()
1338 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in comphy_sfi_power_up()
1341 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in comphy_sfi_power_up()
1343 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_sfi_power_up()
1346 mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; in comphy_sfi_power_up()
1348 mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; in comphy_sfi_power_up()
1350 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_sfi_power_up()
1353 mask = HPIPE_TRAIN_PAT_NUM_MASK; in comphy_sfi_power_up()
1355 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1358 mask = HPIPE_DME_ETHERNET_MODE_MASK; in comphy_sfi_power_up()
1360 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in comphy_sfi_power_up()
1363 mask = HPIPE_CAL_VDD_CONT_MODE_MASK; in comphy_sfi_power_up()
1365 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in comphy_sfi_power_up()
1368 mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; in comphy_sfi_power_up()
1370 mask |= HPIPE_SMAPLER_MASK; in comphy_sfi_power_up()
1372 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1373 mask = HPIPE_SMAPLER_MASK; in comphy_sfi_power_up()
1375 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1378 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in comphy_sfi_power_up()
1380 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sfi_power_up()
1384 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sfi_power_up()
1386 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sfi_power_up()
1388 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sfi_power_up()
1390 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1397 mask = data; in comphy_sfi_power_up()
1398 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sfi_power_up()
1408 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sfi_power_up()
1410 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1416 mask = data; in comphy_sfi_power_up()
1417 data = polling_with_timeout(addr, data, mask, 100); in comphy_sfi_power_up()
1427 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sfi_power_up()
1429 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sfi_power_up()
1431 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1440 u32 mask, data, ret = 1; in comphy_rxauii_power_up() local
1449 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_rxauii_power_up()
1451 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_rxauii_power_up()
1453 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_rxauii_power_up()
1467 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_rxauii_power_up()
1469 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in comphy_rxauii_power_up()
1471 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in comphy_rxauii_power_up()
1473 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_rxauii_power_up()
1475 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_rxauii_power_up()
1477 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in comphy_rxauii_power_up()
1479 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; in comphy_rxauii_power_up()
1481 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1484 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_rxauii_power_up()
1486 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_rxauii_power_up()
1488 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_rxauii_power_up()
1490 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1492 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_rxauii_power_up()
1494 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_rxauii_power_up()
1496 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1508 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_rxauii_power_up()
1510 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_rxauii_power_up()
1512 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_rxauii_power_up()
1517 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in comphy_rxauii_power_up()
1519 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in comphy_rxauii_power_up()
1521 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_rxauii_power_up()
1541 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_rxauii_power_up()
1543 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_rxauii_power_up()
1545 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in comphy_rxauii_power_up()
1547 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_rxauii_power_up()
1549 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in comphy_rxauii_power_up()
1551 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in comphy_rxauii_power_up()
1553 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_rxauii_power_up()
1556 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in comphy_rxauii_power_up()
1558 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_rxauii_power_up()
1562 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_rxauii_power_up()
1564 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_rxauii_power_up()
1566 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_rxauii_power_up()
1568 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1575 mask = data; in comphy_rxauii_power_up()
1576 data = polling_with_timeout(addr, data, mask, 15000); in comphy_rxauii_power_up()
1594 mask = data; in comphy_rxauii_power_up()
1595 data = polling_with_timeout(addr, data, mask, 100); in comphy_rxauii_power_up()
1605 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_rxauii_power_up()
1607 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_rxauii_power_up()
1609 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1620 u32 mask, data; in comphy_utmi_power_down() local
1637 mask = UTMI_USB_CFG_DEVICE_EN_MASK; in comphy_utmi_power_down()
1640 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; in comphy_utmi_power_down()
1642 reg_set(usb_cfg_addr, data, mask); in comphy_utmi_power_down()
1646 mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; in comphy_utmi_power_down()
1649 mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; in comphy_utmi_power_down()
1651 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); in comphy_utmi_power_down()
1665 u32 mask, data; in comphy_utmi_phy_config() local
1670 mask = UTMI_PLL_CTRL_REFDIV_MASK; in comphy_utmi_phy_config()
1673 mask |= UTMI_PLL_CTRL_FBDIV_MASK; in comphy_utmi_phy_config()
1676 mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; in comphy_utmi_phy_config()
1678 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1686 mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; in comphy_utmi_phy_config()
1689 mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; in comphy_utmi_phy_config()
1691 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1694 mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; in comphy_utmi_phy_config()
1697 mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; in comphy_utmi_phy_config()
1699 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); in comphy_utmi_phy_config()
1702 mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; in comphy_utmi_phy_config()
1705 mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; in comphy_utmi_phy_config()
1707 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); in comphy_utmi_phy_config()
1710 mask = UTMI_CHGDTC_CTRL_VDAT_MASK; in comphy_utmi_phy_config()
1713 mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; in comphy_utmi_phy_config()
1715 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1725 u32 data, mask, ret = 1; in comphy_utmi_power_up() local
1742 mask = data; in comphy_utmi_power_up()
1743 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1751 mask = data; in comphy_utmi_power_up()
1752 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1761 mask = data; in comphy_utmi_power_up()
1762 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()