74 #define PHY_BASE(unit)		((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE)  argument
75 #define PHY_SHFT(unit)		((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)  argument
84 #define PWR_PLL_CTRL_ADDR(unit)		\  argument
85 	(PHY_PWR_PLL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
94 #define KVCO_CAL_CTRL_ADDR(unit)	\  argument
95 	(PHY_REG_KVCO_CAL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
101 #define DIG_LB_EN_ADDR(unit)		\  argument
102 	(PHY_DIG_LB_EN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
108 #define SYNC_PATTERN_ADDR(unit)		\  argument
109 	(PHY_SYNC_PATTERN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
115 #define UNIT_CTRL_ADDR(unit)		\  argument
116 	(PHY_REG_UNIT_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
121 #define GEN2_SETTING_2_ADDR(unit)	\  argument
122 	(PHY_REG_GEN2_SETTINGS_2 * PHY_SHFT(unit) + PHY_BASE(unit))
127 #define GEN2_SETTING_3_ADDR(unit)	\  argument
128 	(PHY_REG_GEN2_SETTINGS_3 * PHY_SHFT(unit) + PHY_BASE(unit))
132 #define MISC_REG0_ADDR(unit)		\  argument
133 	(PHY_MISC_REG0_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
140 #define UNIT_IFACE_REF_CLK_CTRL_ADDR(unit)	\  argument
141 	(PHY_REG_IFACE_REF_CLK_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
148 #define UNIT_ERR_CNT_CONST_CTRL_ADDR(unit) \  argument
149 	(PHY_REG_ERR_CNT_CONST_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))