Lines Matching +full:0 +full:xd8000
19 #define POLL_32B_REG 0
24 #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
25 #define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0))
27 #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28)
36 #define rf_gen_rx_select (0x0F << rf_gen_rx_sel_shift)
38 #define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift)
41 #define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28)
42 #define rb_rx_init_done BIT(0)
49 #define PCIE_BASE MVEBU_REG(0x070000)
50 #define PCIETOP_BASE MVEBU_REG(0x080000)
51 #define PCIE_RAMBASE MVEBU_REG(0x08C000)
52 #define PCIEPHY_BASE MVEBU_REG(0x01F000)
55 #define USB32_BASE MVEBU_REG(0x050000) /* usb3 device */
56 #define USB32H_BASE MVEBU_REG(0x058000) /* usb3 host */
57 #define USB3PHY_BASE MVEBU_REG(0x05C000)
58 #define USB2PHY_BASE MVEBU_REG(0x05D000)
59 #define USB2PHY2_BASE MVEBU_REG(0x05F000)
60 #define USB32_CTRL_BASE MVEBU_REG(0x05D800)
64 #define SGMIIPHY_ADDR(l, a) (((a & 0x00007FF) * 2) | SGMIIPHY_BASE(l))
78 #define usb32_ctrl_id_mode BIT(0)
83 #define PHY_PWR_PLL_CTRL_ADDR 0x01 /* for phy_read16 and phy_write16 */
87 #define rf_phy_mode_mask (0x7 << rf_phy_mode_shift)
88 #define rf_ref_freq_sel_shift 0
89 #define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift)
90 #define PHY_MODE_SGMII 0x4
93 #define PHY_REG_KVCO_CAL_CTRL_ADDR 0x02
100 #define PHY_DIG_LB_EN_ADDR 0x23
104 #define rf_data_width_mask (0x3 << rf_data_width_shift)
107 #define PHY_SYNC_PATTERN_ADDR 0x24
114 #define PHY_REG_UNIT_CTRL_ADDR 0x48
120 #define PHY_REG_GEN2_SETTINGS_2 0x3e
126 #define PHY_REG_GEN2_SETTINGS_3 0x3f
131 #define PHY_MISC_REG0_ADDR 0x4f
139 #define PHY_REG_IFACE_REF_CLK_CTRL_ADDR 0x51
143 #define rf_ref1m_gen_div_value_shift 0
144 #define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift)
147 #define PHY_REG_ERR_CNT_CONST_CTRL_ADDR 0x6A
152 #define MISC_REG1_ADDR(u) (0x73 * PHY_SHFT(u) + PHY_BASE(u))
155 #define LANE_CFG0_ADDR(u) (0x180 * PHY_SHFT(u) + PHY_BASE(u))
157 #define LANE_CFG1_ADDR(u) (0x181 * PHY_SHFT(u) + PHY_BASE(u))
159 /* 0x5c310 = 0x93 (set BIT7) */
160 #define LANE_CFG4_ADDR(u) (0x188 * PHY_SHFT(u) + PHY_BASE(u))
163 #define LANE_STAT1_ADDR(u) (0x183 * PHY_SHFT(u) + PHY_BASE(u))
164 #define rb_txdclk_pclk_en BIT(0)
166 #define GLOB_PHY_CTRL0_ADDR(u) (0x1c1 * PHY_SHFT(u) + PHY_BASE(u))
167 #define bf_soft_rst BIT(0)
168 #define bf_mode_refdiv 0x30
172 #define TEST_MODE_CTRL_ADDR(u) (0x1c2 * PHY_SHFT(u) + PHY_BASE(u))
175 #define GLOB_CLK_SRC_LO_ADDR(u) (0x1c3 * PHY_SHFT(u) + PHY_BASE(u))
178 #define PWR_MGM_TIM1_ADDR(u) (0x1d0 * PHY_SHFT(u) + PHY_BASE(u))
180 #define PHY_REF_CLK_ADDR (0x4814 + PCIE_BASE)
182 #define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE)
183 #define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE)
184 #define rb_usb3_ctr_100ns 0xff000000
186 #define USB2_OTG_PHY_CTRL_ADDR (0x820 + USB2PHY_BASE)
188 #define rb_usb2phy_pu BIT(0)
190 #define USB2_PHY_OTG_CTRL_ADDR (0x34 + USB2PHY_BASE)
193 #define USB2_PHY_CHRGR_DET_ADDR (0x38 + USB2PHY_BASE)
202 #define USB2_CAL_CTRL_ADDR (0x8 + USB2PHY_BASE)
206 #define USB2_PLL_CTRL0_ADDR (0x0 + USB2PHY_BASE)
209 #define USB2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY_BASE)
212 #define USB2_PHY2_CTRL_ADDR (0x804 + USB2PHY2_BASE)
214 #define rb_usb2phy2_pu BIT(0)
215 #define USB2_PHY2_CAL_CTRL_ADDR (0x8 + USB2PHY2_BASE)
216 #define USB2_PHY2_PLL_CTRL0_ADDR (0x0 + USB2PHY2_BASE)
217 #define USB2_PHY2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY2_BASE)
219 #define USB2_PHY_BASE(usb32) (usb32 == 0 ? USB2PHY2_BASE : USB2PHY_BASE)
221 (usb32 == 0 ? USB2_PHY2_CTRL_ADDR : USB2_OTG_PHY_CTRL_ADDR)
223 (usb32 == 0 ? rb_usb2phy2_suspm : rb_usb2phy_suspm)
225 (usb32 == 0 ? rb_usb2phy2_pu : rb_usb2phy_pu)
227 (usb32 == 0 ? USB2_PHY2_CAL_CTRL_ADDR : USB2_CAL_CTRL_ADDR)
229 (usb32 == 0 ? USB2_PHY2_RX_CHAN_CTRL1_ADDR : USB2_RX_CHAN_CTRL1_ADDR)
231 (usb32 == 0 ? USB2_PHY2_PLL_CTRL0_ADDR : USB2_PLL_CTRL0_ADDR)
236 #define AHCI_BASE MVEBU_REG(0xE0000)
238 #define rh_vsreg_addr (AHCI_BASE + 0x178)
239 #define rh_vsreg_data (AHCI_BASE + 0x17C)
240 #define rh_vs0_a (AHCI_BASE + 0xA0)
241 #define rh_vs0_d (AHCI_BASE + 0xA4)
243 #define vphy_sync_pattern_reg 0x224
247 #define vphy_loopback_reg0 0x223
248 #define bs_phyintf_40bit 0x0C00
249 #define bs_pll_ready_tx 0x10
251 #define vphy_power_reg0 0x201
253 #define vphy_calctl_reg 0x202
256 #define vphy_reserve_reg 0x0e
259 #define vsata_ctrl_reg 0x00
265 #define SDIO_BASE MVEBU_REG(0xD8000)
267 #define SDIO_HOST_CTRL1_ADDR (SDIO_BASE + 0x28)
268 #define SDIO_SDHC_FIFO_ADDR (SDIO_BASE + 0x12C)
269 #define SDIO_CAP_12_ADDR (SDIO_BASE + 0x40)
270 #define SDIO_ENDIAN_ADDR (SDIO_BASE + 0x1A4)
271 #define SDIO_PHY_TIMING_ADDR (SDIO_BASE + 0x170)
272 #define SDIO_PHY_PAD_CTRL0_ADDR (SDIO_BASE + 0x178)
273 #define SDIO_DLL_RST_ADDR (SDIO_BASE + 0x148)