179 	reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);  in comphy_pcie_power_up()
251 	reg_set((void __iomem *)rh_vsreg_addr,  in comphy_sata_power_up()
253 	reg_set((void __iomem *)rh_vsreg_data, bs_txd_inv, bs_txd_inv);  in comphy_sata_power_up()
258 	reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);  in comphy_sata_power_up()
259 	reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit);  in comphy_sata_power_up()
264 	reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF);  in comphy_sata_power_up()
266 		reg_set((void __iomem *)rh_vsreg_data,  in comphy_sata_power_up()
269 		reg_set((void __iomem *)rh_vsreg_data,  in comphy_sata_power_up()
276 	reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF);  in comphy_sata_power_up()
277 	reg_set((void __iomem *)rh_vsreg_data,  in comphy_sata_power_up()
283 	reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF);  in comphy_sata_power_up()
284 	reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin);  in comphy_sata_power_up()
289 	reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);  in comphy_sata_power_up()
290 	reg_set((void __iomem *)rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll);  in comphy_sata_power_up()
296 	reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);  in comphy_sata_power_up()
324 	reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);  in comphy_usb3_power_up()
330 	reg_set((void __iomem *)USB3_CTRPUL_VAL_REG,  in comphy_usb3_power_up()
458 		reg_set((void __iomem *)USB32_CTRL_BASE,  in comphy_usb3_power_up()
492 		reg_set((void __iomem *)USB2_PHY_BASE(usb32),  in comphy_usb2_power_up()
499 	reg_set((void __iomem *)USB2_PHY_CTRL_ADDR(usb32),  in comphy_usb2_power_up()
506 		reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);  in comphy_usb2_power_up()
511 		reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0,  in comphy_usb2_power_up()
570 	reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);  in comphy_emmc_power_up()
575 	reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);  in comphy_emmc_power_up()
580 	reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);  in comphy_emmc_power_up()
585 	reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0);  in comphy_emmc_power_up()
590 	reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);  in comphy_emmc_power_up()
591 	reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000,  in comphy_emmc_power_up()
597 	reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);  in comphy_emmc_power_up()
598 	reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0);  in comphy_emmc_power_up()
653 	reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane));  in comphy_sgmii_power_up()
661 	reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
669 	reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
677 		reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
683 		reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
788 	reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
807 	reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
818 	reg_set((void __iomem *)COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init,  in comphy_sgmii_power_up()