144 	reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE),  in comphy_pcie_power_up()
150 	reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE),  in comphy_pcie_power_up()
156 	reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE),  in comphy_pcie_power_up()
162 	reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF);  in comphy_pcie_power_up()
167 	reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE),  in comphy_pcie_power_up()
173 	reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE),  in comphy_pcie_power_up()
186 		reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),  in comphy_pcie_power_up()
189 		reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE),  in comphy_pcie_power_up()
196 	reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE),  in comphy_pcie_power_up()
203 		reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),  in comphy_pcie_power_up()
208 		reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE),  in comphy_pcie_power_up()
215 	reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(PCIE),  in comphy_pcie_power_up()
223 	ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(PCIE),	/* address */  in comphy_pcie_power_up()