Lines Matching +full:usb3 +full:- +full:if
2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
36 /*-----------------------------------------------------------*/
114 for (; timeout > 0; timeout--) { in comphy_poll_reg()
115 if (op_type == POLL_16B_REG) in comphy_poll_reg()
120 if ((rval & mask) == val) in comphy_poll_reg()
133 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
185 if (get_ref_clk() == 40) { in comphy_pcie_power_up()
202 if (invert & PHY_POLARITY_TXD_INVERT) { in comphy_pcie_power_up()
207 if (invert & PHY_POLARITY_RXD_INVERT) { in comphy_pcie_power_up()
228 if (ret == 0) in comphy_pcie_power_up()
240 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
256 * 1. Select 40-bit data width width in comphy_sata_power_up()
265 if (get_ref_clk() == 40) { in comphy_sata_power_up()
287 * 5. Set vendor-specific configuration (??) in comphy_sata_power_up()
302 if (ret == 0) in comphy_sata_power_up()
313 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
327 * 2. Set counter for 100us pulse in USB3 Host and Device in comphy_usb3_power_up()
335 /* set PRD_TXDEEMPH (3.5db de-emph) */ in comphy_usb3_power_up()
336 reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF); in comphy_usb3_power_up()
344 reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF); in comphy_usb3_power_up()
348 reg_set16((void __iomem *)LANE_CFG4_ADDR(USB3), in comphy_usb3_power_up()
355 reg_set16((void __iomem *)TEST_MODE_CTRL_ADDR(USB3), in comphy_usb3_power_up()
358 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ in comphy_usb3_power_up()
360 reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF); in comphy_usb3_power_up()
363 reg_set16((void __iomem *)GEN2_SETTING_2_ADDR(USB3), g2_tx_ssc_amp, in comphy_usb3_power_up()
370 reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF); in comphy_usb3_power_up()
376 if (get_ref_clk() == 40) { in comphy_usb3_power_up()
377 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3, in comphy_usb3_power_up()
380 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2, in comphy_usb3_power_up()
387 reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF); in comphy_usb3_power_up()
392 reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en, in comphy_usb3_power_up()
398 reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en, in comphy_usb3_power_up()
402 * 7. Set 20-bit data width in comphy_usb3_power_up()
404 reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF); in comphy_usb3_power_up()
409 reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(USB3), in comphy_usb3_power_up()
415 if (invert & PHY_POLARITY_TXD_INVERT) { in comphy_usb3_power_up()
416 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), in comphy_usb3_power_up()
420 if (invert & PHY_POLARITY_RXD_INVERT) { in comphy_usb3_power_up()
421 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(USB3), in comphy_usb3_power_up()
428 reg_set16((void __iomem *)GLOB_PHY_CTRL0_ADDR(USB3), in comphy_usb3_power_up()
436 ret = comphy_poll_reg((void *)LANE_STAT1_ADDR(USB3), /* address */ in comphy_usb3_power_up()
441 if (ret == 0) in comphy_usb3_power_up()
442 printf("Failed to lock USB3 PLL\n"); in comphy_usb3_power_up()
448 if (type == PHY_TYPE_USB3_HOST0) { in comphy_usb3_power_up()
472 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
480 if (usb32 != 0 && usb32 != 1) { in comphy_usb2_power_up()
491 if (get_ref_clk() == 25) { in comphy_usb2_power_up()
502 if (usb32 != 0) { in comphy_usb2_power_up()
522 if (ret == 0) in comphy_usb2_power_up()
531 if (ret == 0) in comphy_usb2_power_up()
540 if (ret == 0) in comphy_usb2_power_up()
550 if (ret == 0) in comphy_usb2_power_up()
561 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
625 if ((speed != PHY_SPEED_1_25G) && in comphy_sgmii_phy_init()
629 if (fix_idx < fix_arr_sz) in comphy_sgmii_phy_init()
642 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
676 if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ in comphy_sgmii_power_up()
682 } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ in comphy_sgmii_power_up()
712 if (get_ref_clk() == 40) { in comphy_sgmii_power_up()
751 * group to get the related GEN table during real chip bring-up. in comphy_sgmii_power_up()
757 debug("Running C-DPI phy init %s mode\n", in comphy_sgmii_power_up()
759 if (get_ref_clk() == 40) in comphy_sgmii_power_up()
776 if (invert & PHY_POLARITY_TXD_INVERT) in comphy_sgmii_power_up()
779 if (invert & PHY_POLARITY_RXD_INVERT) in comphy_sgmii_power_up()
801 if (ret == 0) in comphy_sgmii_power_up()
826 if (ret == 0) in comphy_sgmii_power_up()
837 const void *blob = gd->fdt_blob; in comphy_dedicated_phys_init()
844 * One is independendent and one is paired with USB3 port (OTG) in comphy_dedicated_phys_init()
846 if (usb32 == 0) { in comphy_dedicated_phys_init()
848 blob, -1, "marvell,armada-3700-ehci"); in comphy_dedicated_phys_init()
851 blob, -1, "marvell,armada3700-xhci"); in comphy_dedicated_phys_init()
854 if (node > 0) { in comphy_dedicated_phys_init()
855 if (fdtdec_get_is_enabled(blob, node)) { in comphy_dedicated_phys_init()
857 if (ret == 0) in comphy_dedicated_phys_init()
870 node = fdt_node_offset_by_compatible(blob, -1, in comphy_dedicated_phys_init()
871 "marvell,armada-3700-ahci"); in comphy_dedicated_phys_init()
872 if (node > 0) { in comphy_dedicated_phys_init()
873 if (fdtdec_get_is_enabled(blob, node)) { in comphy_dedicated_phys_init()
875 if (ret == 0) in comphy_dedicated_phys_init()
886 node = fdt_node_offset_by_compatible(blob, -1, in comphy_dedicated_phys_init()
887 "marvell,armada-8k-sdhci"); in comphy_dedicated_phys_init()
888 if (node <= 0) { in comphy_dedicated_phys_init()
890 blob, -1, "marvell,armada-3700-sdhci"); in comphy_dedicated_phys_init()
893 if (node > 0) { in comphy_dedicated_phys_init()
894 if (fdtdec_get_is_enabled(blob, node)) { in comphy_dedicated_phys_init()
896 if (ret == 0) in comphy_dedicated_phys_init()
914 u32 comphy_max_count = chip_cfg->comphy_lanes_count; in comphy_a3700_init()
923 comphy_map->type, comphy_map->invert); in comphy_a3700_init()
925 switch (comphy_map->type) { in comphy_a3700_init()
931 ret = comphy_pcie_power_up(comphy_map->speed, in comphy_a3700_init()
932 comphy_map->invert); in comphy_a3700_init()
937 ret = comphy_usb3_power_up(comphy_map->type, in comphy_a3700_init()
938 comphy_map->speed, in comphy_a3700_init()
939 comphy_map->invert); in comphy_a3700_init()
944 ret = comphy_sgmii_power_up(lane, comphy_map->speed, in comphy_a3700_init()
945 comphy_map->invert); in comphy_a3700_init()
954 if (ret == 0) in comphy_a3700_init()
955 printf("PLL is not locked - Failed to initialize lane %d\n", in comphy_a3700_init()