2  * Copyright (C) 2015-2016 Marvell International Ltd.
4  * SPDX-License-Identifier:	GPL-2.0+
36 	/*-----------------------------------------------------------*/
114 	for (; timeout > 0; timeout--) {  in comphy_poll_reg()
135 static int comphy_pcie_power_up(u32 speed, u32 invert)  in comphy_pcie_power_up()  argument
142 	 * 1. Enable max PLL.  in comphy_pcie_power_up()
165 	 * 5. Enable idle sync  in comphy_pcie_power_up()
171 	 * 6. Enable the output of 100M/125M/500M clock  in comphy_pcie_power_up()
177 	 * 7. Enable TX  in comphy_pcie_power_up()
200 	 * 10. Check the Polarity invert bit  in comphy_pcie_power_up()
202 	if (invert & PHY_POLARITY_TXD_INVERT) {  in comphy_pcie_power_up()
207 	if (invert & PHY_POLARITY_RXD_INVERT) {  in comphy_pcie_power_up()
256 	 * 1. Select 40-bit data width width  in comphy_sata_power_up()
287 	 * 5. Set vendor-specific configuration (??)  in comphy_sata_power_up()
315 static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)  in comphy_usb3_power_up()  argument
335 	/* set PRD_TXDEEMPH (3.5db de-emph) */  in comphy_usb3_power_up()
358 	/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */  in comphy_usb3_power_up()
390 	 * 5. Enable idle sync  in comphy_usb3_power_up()
396 	 * 6. Enable the output of 500M clock  in comphy_usb3_power_up()
402 	 * 7. Set 20-bit data width  in comphy_usb3_power_up()
413 	 * 9. Check the Polarity invert bit  in comphy_usb3_power_up()
415 	if (invert & PHY_POLARITY_TXD_INVERT) {  in comphy_usb3_power_up()
420 	if (invert & PHY_POLARITY_RXD_INVERT) {  in comphy_usb3_power_up()
452 		 * set   BIT4: set INT_MODE = ID. Interrupt Mode: enable  in comphy_usb3_power_up()
644 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)  in comphy_sgmii_power_up()  argument
751 	 *     group to get the related GEN table during real chip bring-up.  in comphy_sgmii_power_up()
757 	debug("Running C-DPI phy init %s mode\n",  in comphy_sgmii_power_up()
774 	 * 18. Check the PHY Polarity invert bit  in comphy_sgmii_power_up()
776 	if (invert & PHY_POLARITY_TXD_INVERT)  in comphy_sgmii_power_up()
779 	if (invert & PHY_POLARITY_RXD_INVERT)  in comphy_sgmii_power_up()
837 	const void *blob = gd->fdt_blob;  in comphy_dedicated_phys_init()
848 				blob, -1, "marvell,armada-3700-ehci");  in comphy_dedicated_phys_init()
851 				blob, -1, "marvell,armada3700-xhci");  in comphy_dedicated_phys_init()
870 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
871 					     "marvell,armada-3700-ahci");  in comphy_dedicated_phys_init()
886 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
887 					     "marvell,armada-8k-sdhci");  in comphy_dedicated_phys_init()
890 			blob, -1, "marvell,armada-3700-sdhci");  in comphy_dedicated_phys_init()
914 	u32 comphy_max_count = chip_cfg->comphy_lanes_count;  in comphy_a3700_init()
922 		debug("Serdes type = 0x%x invert=%d\n",  in comphy_a3700_init()
923 		      comphy_map->type, comphy_map->invert);  in comphy_a3700_init()
925 		switch (comphy_map->type) {  in comphy_a3700_init()
931 			ret = comphy_pcie_power_up(comphy_map->speed,  in comphy_a3700_init()
932 						   comphy_map->invert);  in comphy_a3700_init()
937 			ret = comphy_usb3_power_up(comphy_map->type,  in comphy_a3700_init()
938 						   comphy_map->speed,  in comphy_a3700_init()
939 						   comphy_map->invert);  in comphy_a3700_init()
944 			ret = comphy_sgmii_power_up(lane, comphy_map->speed,  in comphy_a3700_init()
945 						    comphy_map->invert);  in comphy_a3700_init()
955 			printf("PLL is not locked - Failed to initialize lane %d\n",  in comphy_a3700_init()