24 	{0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
25 	{0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
26 	{0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
27 	{0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
28 	{0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
29 	{0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
30 	{0x104, 0x0C10}
35 	/* 0       1       2       3       4       5       6       7 */
38 	0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26,	/* 00 */
39 	0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52,	/* 08 */
40 	0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000,	/* 10 */
41 	0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF,	/* 18 */
42 	0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000,	/* 20 */
43 	0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,	/* 28 */
44 	0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/* 30 */
45 	0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100,	/* 38 */
46 	0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00,	/* 40 */
47 	0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A,	/* 48 */
48 	0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001,	/* 50 */
49 	0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF,	/* 58 */
50 	0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000,	/* 60 */
51 	0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002,	/* 68 */
52 	0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780,	/* 70 */
53 	0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000,	/* 78 */
54 	0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000,	/* 80 */
55 	0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210,	/* 88 */
56 	0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F,	/* 90 */
57 	0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651,	/* 98 */
58 	0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000,	/* A0 */
59 	0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/* A8 */
60 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/* B0 */
61 	0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000,	/* B8 */
62 	0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003,	/* C0 */
63 	0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000,	/* C8 */
64 	0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00,	/* D0 */
65 	0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000,	/* D8 */
66 	0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541,	/* E0 */
67 	0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200,	/* E8 */
68 	0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000,	/* F0 */
69 	0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000,	/* F8 */
70 	0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000,	/*100 */
71 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*108 */
72 	0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000,	/*110 */
73 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*118 */
74 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*120 */
75 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*128 */
76 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*130 */
77 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*138 */
78 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*140 */
79 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*148 */
80 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*150 */
81 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*158 */
82 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*160 */
83 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*168 */
84 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*170 */
85 	0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000,	/*178 */
86 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*180 */
87 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*188 */
88 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*190 */
89 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*198 */
90 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1A0 */
91 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1A8 */
92 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1B0 */
93 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1B8 */
94 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1C0 */
95 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1C8 */
96 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1D0 */
97 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1D8 */
98 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1E0 */
99 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1E8 */
100 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,	/*1F0 */
101 	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000	/*1F8 */
107  * return: 1 on success, 0 on timeout
112 	u32 rval = 0xDEAD;  in comphy_poll_reg()
114 	for (; timeout > 0; timeout--) {  in comphy_poll_reg()
127 	return 0;  in comphy_poll_reg()
133  * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
145 		  bf_use_max_pll_rate, 0);  in comphy_pcie_power_up()
151 		  bf_cfg_sel_20b, 0);  in comphy_pcie_power_up()
157 		  bf_sel_bits_pcie_force, 0);  in comphy_pcie_power_up()
162 	reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF);  in comphy_pcie_power_up()
168 		  0x60 | rb_idle_sync_en, 0xFFFF);  in comphy_pcie_power_up()
174 		  0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);  in comphy_pcie_power_up()
179 	reg_set((void __iomem *)PHY_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);  in comphy_pcie_power_up()
187 			  0xFC63, 0xFFFF); /* 40 MHz */  in comphy_pcie_power_up()
190 			  0xFC62, 0xFFFF); /* 25 MHz */  in comphy_pcie_power_up()
197 		  0x0040 | rb_use_max_pll_rate, 0xFFFF);  in comphy_pcie_power_up()
204 			  phy_txd_inv, 0);  in comphy_pcie_power_up()
209 			  phy_rxd_inv, 0);  in comphy_pcie_power_up()
228 	if (ret == 0)  in comphy_pcie_power_up()
240  * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
249 	 * 0. Swap SATA TX lines  in comphy_sata_power_up()
252 		vphy_sync_pattern_reg, 0xFFFFFFFF);  in comphy_sata_power_up()
258 	reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);  in comphy_sata_power_up()
259 	reg_set((void __iomem *)rh_vsreg_data, 0x800, bs_phyintf_40bit);  in comphy_sata_power_up()
264 	reg_set((void __iomem *)rh_vsreg_addr, vphy_power_reg0, 0xFFFFFFFF);  in comphy_sata_power_up()
267 			0x3, 0x00FF); /* 40 MHz */  in comphy_sata_power_up()
270 			0x1, 0x00FF); /* 25 MHz */  in comphy_sata_power_up()
276 	reg_set((void __iomem *)rh_vsreg_addr, vphy_calctl_reg, 0xFFFFFFFF);  in comphy_sata_power_up()
283 	reg_set((void __iomem *)rh_vsreg_addr, vphy_reserve_reg, 0xFFFFFFFF);  in comphy_sata_power_up()
284 	reg_set((void __iomem *)rh_vsreg_data, 0, bs_phyctrl_frm_pin);  in comphy_sata_power_up()
289 	reg_set((void __iomem *)rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);  in comphy_sata_power_up()
296 	reg_set((void __iomem *)rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);  in comphy_sata_power_up()
302 	if (ret == 0)  in comphy_sata_power_up()
313  * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
324 	reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);  in comphy_usb3_power_up()
331 		0x8 << 24, rb_usb3_ctr_100ns);  in comphy_usb3_power_up()
334 	/* 0xd005c300 = 0x1001 */  in comphy_usb3_power_up()
336 	reg_set16((void __iomem *)LANE_CFG0_ADDR(USB3), 0x1, 0xFF);  in comphy_usb3_power_up()
344 	reg_set16((void __iomem *)LANE_CFG1_ADDR(USB3), 0x0, 0xFFFF);  in comphy_usb3_power_up()
347 	/* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled  */  in comphy_usb3_power_up()
349 		  bf_spread_spectrum_clock_en, 0x80);  in comphy_usb3_power_up()
356 		  rb_mode_margin_override, 0xFFFF);  in comphy_usb3_power_up()
360 	reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(USB3), 0x0, 0xFF);  in comphy_usb3_power_up()
364 		  0xF000);  in comphy_usb3_power_up()
370 	reg_set16((void __iomem *)GEN2_SETTING_3_ADDR(USB3), 0x0, 0xFFFF);  in comphy_usb3_power_up()
377 		reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA3,  in comphy_usb3_power_up()
378 			  0xFFFF); /* 40 MHz */  in comphy_usb3_power_up()
380 		reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(USB3), 0xFCA2,  in comphy_usb3_power_up()
381 			  0xFFFF); /* 25 MHz */  in comphy_usb3_power_up()
387 	reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(USB3), 0x10C, 0xFFFF);  in comphy_usb3_power_up()
392 	reg_set16((void __iomem *)UNIT_CTRL_ADDR(USB3), 0x60 | rb_idle_sync_en,  in comphy_usb3_power_up()
393 		  0xFFFF);  in comphy_usb3_power_up()
398 	reg_set16((void __iomem *)MISC_REG0_ADDR(USB3), 0xA00D | rb_clk500m_en,  in comphy_usb3_power_up()
399 		  0xFFFF);  in comphy_usb3_power_up()
404 	reg_set16((void __iomem *)DIG_LB_EN_ADDR(USB3), 0x0400, 0xFFFF);  in comphy_usb3_power_up()
410 		  0x0040 | rb_use_max_pll_rate, 0xFFFF);  in comphy_usb3_power_up()
417 			  phy_txd_inv, 0);  in comphy_usb3_power_up()
422 			  phy_rxd_inv, 0);  in comphy_usb3_power_up()
429 		  rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32 | 0x20,  in comphy_usb3_power_up()
430 		  0xFFFF);  in comphy_usb3_power_up()
441 	if (ret == 0)  in comphy_usb3_power_up()
472  * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
480 	if (usb32 != 0 && usb32 != 1) {  in comphy_usb2_power_up()
481 		printf("invalid usb32 value: (%d), should be either 0 or 1\n",  in comphy_usb2_power_up()
484 		return 0;  in comphy_usb2_power_up()
488 	 * 0. Setup PLL. 40MHz clock uses defaults.  in comphy_usb2_power_up()
493 			5 | (96 << 16), 0x3F | (0xFF << 16) | (0x3 << 28));  in comphy_usb2_power_up()
500 		RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0);  in comphy_usb2_power_up()
502 	if (usb32 != 0) {  in comphy_usb2_power_up()
506 		reg_set((void __iomem *)USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);  in comphy_usb2_power_up()
511 		reg_set((void __iomem *)USB2_PHY_CHRGR_DET_ADDR, 0,  in comphy_usb2_power_up()
522 	if (ret == 0)  in comphy_usb2_power_up()
531 	if (ret == 0)  in comphy_usb2_power_up()
540 	if (ret == 0)  in comphy_usb2_power_up()
550 	if (ret == 0)  in comphy_usb2_power_up()
561  * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
570 	reg_set((void __iomem *)SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);  in comphy_emmc_power_up()
575 	reg_set((void __iomem *)SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);  in comphy_emmc_power_up()
580 	reg_set((void __iomem *)SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);  in comphy_emmc_power_up()
585 	reg_set((void __iomem *)SDIO_ENDIAN_ADDR, 0x00c00000, 0);  in comphy_emmc_power_up()
590 	reg_set((void __iomem *)SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);  in comphy_emmc_power_up()
591 	reg_set((void __iomem *)SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000,  in comphy_emmc_power_up()
592 		0xF0000000);  in comphy_emmc_power_up()
597 	reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);  in comphy_emmc_power_up()
598 	reg_set((void __iomem *)SDIO_DLL_RST_ADDR, 0x00010000, 0);  in comphy_emmc_power_up()
616 	fix_idx = 0;  in comphy_sgmii_phy_init()
617 	for (addr = 0; addr < 512; addr++) {  in comphy_sgmii_phy_init()
635 		phy_write16(lane, addr, val, 0xFFFF);  in comphy_sgmii_phy_init()
642  * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
651 	 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0  in comphy_sgmii_power_up()
653 	reg_set((void __iomem *)COMPHY_SEL_ADDR, 0, rf_compy_select(lane));  in comphy_sgmii_power_up()
659 	 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.  in comphy_sgmii_power_up()
667 	 * 5. Release reset to the PHY by setting PIN_RESET=0.  in comphy_sgmii_power_up()
670 		0, rb_pin_reset_comphy);  in comphy_sgmii_power_up()
673 	 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide  in comphy_sgmii_power_up()
678 			(0x8 << rf_gen_rx_sel_shift) |  in comphy_sgmii_power_up()
679 			(0x8 << rf_gen_tx_sel_shift),  in comphy_sgmii_power_up()
684 			(0x6 << rf_gen_rx_sel_shift) |  in comphy_sgmii_power_up()
685 			(0x6 << rf_gen_tx_sel_shift),  in comphy_sgmii_power_up()
689 		return 0;  in comphy_sgmii_power_up()
706 	phy_write16(lane, PHY_MISC_REG0_ADDR, 0, rb_ref_clk_sel);  in comphy_sgmii_power_up()
714 			    0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);  in comphy_sgmii_power_up()
718 			    0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);  in comphy_sgmii_power_up()
721 	/* 12. Program COMPHY register PHY_GEN_MAX[1:0] */  in comphy_sgmii_power_up()
734 	phy_write16(lane, PHY_DIG_LB_EN_ADDR, 0, rf_data_width_mask);  in comphy_sgmii_power_up()
738 	 *     COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F  in comphy_sgmii_power_up()
744 	 * specification DFE_UPDATE_EN already has the default value 0x3F  in comphy_sgmii_power_up()
777 		phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_txd_inv, 0);  in comphy_sgmii_power_up()
780 		phy_write16(lane, PHY_SYNC_PATTERN_ADDR, phy_rxd_inv, 0);  in comphy_sgmii_power_up()
801 	if (ret == 0)  in comphy_sgmii_power_up()
805 	 * 21. Set COMPHY input port PIN_TX_IDLE=0  in comphy_sgmii_power_up()
808 		0x0, rb_pin_tx_idle);  in comphy_sgmii_power_up()
813 	 *     0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE  in comphy_sgmii_power_up()
814 	 *     will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after  in comphy_sgmii_power_up()
819 		0x0);  in comphy_sgmii_power_up()
826 	if (ret == 0)  in comphy_sgmii_power_up()
841 	for (usb32 = 0; usb32 <= 1; usb32++) {  in comphy_dedicated_phys_init()
846 		if (usb32 == 0) {  in comphy_dedicated_phys_init()
854 		if (node > 0) {  in comphy_dedicated_phys_init()
857 				if (ret == 0)  in comphy_dedicated_phys_init()
863 				      usb32 == 0 ? 2 : 3);  in comphy_dedicated_phys_init()
866 			debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3);  in comphy_dedicated_phys_init()
872 	if (node > 0) {  in comphy_dedicated_phys_init()
875 			if (ret == 0)  in comphy_dedicated_phys_init()
888 	if (node <= 0) {  in comphy_dedicated_phys_init()
893 	if (node > 0) {  in comphy_dedicated_phys_init()
896 			if (ret == 0)  in comphy_dedicated_phys_init()
915 	u32 lane, ret = 0;  in comphy_a3700_init()
919 	for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;  in comphy_a3700_init()
922 		debug("Serdes type = 0x%x invert=%d\n",  in comphy_a3700_init()
954 		if (ret == 0)  in comphy_a3700_init()