Lines Matching +full:de +full:- +full:asserting
2 * Freescale i.MX6 PCI Express Root-Complex driver
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
7 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
8 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
10 * SPDX-License-Identifier: GPL-2.0
43 /* PCIe Port Logic registers (memory-mapped) */
64 /* PHY registers (not memory-mapped) */
116 return -ETIMEDOUT; in pcie_phy_poll_ack()
144 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
201 /* wait for ack de-assertion */ in pcie_phy_write()
219 /* wait for ack de-assertion */ in pcie_phy_write()
238 return -EAGAIN; in imx6_pcie_link_up()
283 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO in imx_pcie_regions_setup()
284 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM in imx_pcie_regions_setup()
285 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers in imx_pcie_regions_setup()
330 va_address = MX6_IO_ADDR + SZ_16M - SZ_1M; in get_bus_address()
341 return -EINVAL; in imx_pcie_addr_valid()
343 return -EINVAL; in imx_pcie_addr_valid()
348 * Replace the original ARM DABT handler with a simple jump-back one.
439 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); in imx6_pcie_assert_core_reset()
445 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); in imx6_pcie_assert_core_reset()
447 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); in imx6_pcie_assert_core_reset()
449 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); in imx6_pcie_assert_core_reset()
465 gpr1 = readl(&iomuxc_regs->gpr[1]); in imx6_pcie_assert_core_reset()
466 gpr12 = readl(&iomuxc_regs->gpr[12]); in imx6_pcie_assert_core_reset()
478 writel(val, &iomuxc_regs->gpr[12]); in imx6_pcie_assert_core_reset()
481 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); in imx6_pcie_assert_core_reset()
482 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); in imx6_pcie_assert_core_reset()
492 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); in imx6_pcie_init_phy()
494 clrsetbits_le32(&iomuxc_regs->gpr[12], in imx6_pcie_init_phy()
497 clrsetbits_le32(&iomuxc_regs->gpr[12], in imx6_pcie_init_phy()
502 clrsetbits_le32(&iomuxc_regs->gpr[12], in imx6_pcie_init_phy()
512 &iomuxc_regs->gpr[8]); in imx6_pcie_init_phy()
536 * least 20 ms after de-asserting the #PERST so the EP device can in imx6_pcie_toggle_reset()
537 * do self-initialisation. in imx6_pcie_toggle_reset()
547 * not forget to wait at least 20 ms after de-asserting #PERST in in imx6_pcie_toggle_reset()
555 * Linux at all in the first place since it's in some non-reset in imx6_pcie_toggle_reset()
556 * state due to being previously used in U-Boot. in imx6_pcie_toggle_reset()
578 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); in imx6_pcie_deassert_core_reset()
588 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); in imx6_pcie_deassert_core_reset()
590 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); in imx6_pcie_deassert_core_reset()
593 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); in imx6_pcie_deassert_core_reset()
594 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); in imx6_pcie_deassert_core_reset()
618 * link is up, a managed Gen1->Gen2 transition can be initiated. in imx_pcie_link_up()
626 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); in imx_pcie_link_up()
638 return -EINVAL; in imx_pcie_link_up()
655 pci_set_region(&hose->regions[0], in imx_pcie_init()
660 pci_set_region(&hose->regions[1], in imx_pcie_init()
665 pci_set_region(&hose->regions[2], in imx_pcie_init()
669 hose->region_count = 3; in imx_pcie_init()
684 hose->last_busno = pci_hose_scan(hose); in imx_pcie_init()