60 	void		*dbi_base;  member
230 	return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) &  in rk_pcie_get_link_speed()
236 	return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) &  in rk_pcie_get_link_width()
244 	void __iomem *base = rk_pcie->dbi_base;  in rk_pcie_writel_ob_unroll()
252 	void __iomem *base = rk_pcie->dbi_base;  in rk_pcie_readl_ob_unroll()
261 	val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF);  in rk_pcie_dbi_write_enable()
267 	writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF);  in rk_pcie_dbi_write_enable()
278 	       rk_pcie->dbi_base + PCI_BASE_ADDRESS_0);  in rk_pcie_setup_host()
279 	writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1);  in rk_pcie_setup_host()
282 	val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE);  in rk_pcie_setup_host()
285 	writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE);  in rk_pcie_setup_host()
288 	val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS);  in rk_pcie_setup_host()
291 	writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS);  in rk_pcie_setup_host()
293 	val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS);  in rk_pcie_setup_host()
296 	val = readl(rk_pcie->dbi_base + PCI_COMMAND);  in rk_pcie_setup_host()
300 	writel(val, rk_pcie->dbi_base + PCI_COMMAND);  in rk_pcie_setup_host()
303 	writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE);  in rk_pcie_setup_host()
306 	val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in rk_pcie_setup_host()
308 	writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in rk_pcie_setup_host()
311 	writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4);  in rk_pcie_setup_host()
312 	writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4);  in rk_pcie_setup_host()
323 	val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);  in rk_pcie_configure()
326 	writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);  in rk_pcie_configure()
328 	val = readl(pci->dbi_base + PCIE_LINK_CTL_2);  in rk_pcie_configure()
331 	writel(val, pci->dbi_base + PCIE_LINK_CTL_2);  in rk_pcie_configure()
394 		va_address = (uintptr_t)pcie->dbi_base;  in set_cfg_address()
687 	priv->dbi_base = (void *)(res.start);  in rockchip_pcie_parse_dt()
688 	dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base);  in rockchip_pcie_parse_dt()