drivers/pci/pci_tegra.c

5  * Based on NVIDIA PCIe driver
13 #define pr_fmt(fmt) "tegra-pcie: " fmt
166  * entries, one entry per PCIe port. These field definitions and desired
197 	struct tegra_pcie *pcie;  member
244 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,  in afi_writel()  argument
247 	writel(value, pcie->afi.start + offset);  in afi_writel()
250 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)  in afi_readl()  argument
252 	return readl(pcie->afi.start + offset);  in afi_readl()
255 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,  in pads_writel()  argument
258 	writel(value, pcie->pads.start + offset);  in pads_writel()
262 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)  in pads_readl()  argument
264 	return readl(pcie->pads.start + offset);  in pads_readl()
287 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,  in tegra_pcie_conf_address()  argument
296 		list_for_each_entry(port, &pcie->ports, list) {  in tegra_pcie_conf_address()
310 		*address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);  in tegra_pcie_conf_address()
319 	struct tegra_pcie *pcie = dev_get_priv(bus);  in pci_tegra_read_config()  local
323 	err = tegra_pcie_conf_address(pcie, bdf, offset, &address);  in pci_tegra_read_config()
351 	struct tegra_pcie *pcie = dev_get_priv(bus);  in pci_tegra_write_config()  local
356 	err = tegra_pcie_conf_address(pcie, bdf, offset, &address);  in pci_tegra_write_config()
488 			       struct tegra_pcie *pcie)  in tegra_pcie_parse_dt()  argument
494 	err = dev_read_resource(dev, 0, &pcie->pads);  in tegra_pcie_parse_dt()
500 	err = dev_read_resource(dev, 1, &pcie->afi);  in tegra_pcie_parse_dt()
506 	err = dev_read_resource(dev, 2, &pcie->cs);  in tegra_pcie_parse_dt()
519 	pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);  in tegra_pcie_parse_dt()
520 	if (pcie->phy) {  in tegra_pcie_parse_dt()
521 		err = tegra_xusb_phy_prepare(pcie->phy);  in tegra_pcie_parse_dt()
558 		list_add_tail(&port->list, &pcie->ports);  in tegra_pcie_parse_dt()
559 		port->pcie = pcie;  in tegra_pcie_parse_dt()
563 					 &pcie->xbar);  in tegra_pcie_parse_dt()
573 static int tegra_pcie_power_on(struct tegra_pcie *pcie)  in tegra_pcie_power_on()  argument
577 	ret = power_domain_on(&pcie->pwrdom);  in tegra_pcie_power_on()
583 	ret = clk_enable(&pcie->clk_afi);  in tegra_pcie_power_on()
589 	ret = clk_enable(&pcie->clk_pex);  in tegra_pcie_power_on()
595 	ret = reset_deassert(&pcie->reset_afi);  in tegra_pcie_power_on()
601 	ret = reset_deassert(&pcie->reset_pex);  in tegra_pcie_power_on()
610 static int tegra_pcie_power_on(struct tegra_pcie *pcie)  in tegra_pcie_power_on()  argument
612 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_power_on()
616 	/* reset PCIEXCLK logic, AFI controller and PCIe controller */  in tegra_pcie_power_on()
623 		pr_err("failed to power off PCIe partition: %d", err);  in tegra_pcie_power_on()
630 		pr_err("failed to power up PCIe partition: %d", err);  in tegra_pcie_power_on()
657 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)  in tegra_pcie_pll_wait()  argument
659 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_pll_wait()
664 		value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_pll_wait()
672 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)  in tegra_pcie_phy_enable()  argument
674 	const struct tegra_pcie_soc *soc = pcie->soc;  in tegra_pcie_phy_enable()
678 	/* initialize internal PHY, enable up to 16 PCIe lanes */  in tegra_pcie_phy_enable()
679 	pads_writel(pcie, 0, PADS_CTL_SEL);  in tegra_pcie_phy_enable()
682 	value = pads_readl(pcie, PADS_CTL);  in tegra_pcie_phy_enable()
684 	pads_writel(pcie, value, PADS_CTL);  in tegra_pcie_phy_enable()
690 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
693 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
696 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
698 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
703 	value = pads_readl(pcie, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
705 	pads_writel(pcie, value, soc->pads_pll_ctl);  in tegra_pcie_phy_enable()
708 	err = tegra_pcie_pll_wait(pcie, 500);  in tegra_pcie_phy_enable()
715 	value = pads_readl(pcie, PADS_CTL);  in tegra_pcie_phy_enable()
717 	pads_writel(pcie, value, PADS_CTL);  in tegra_pcie_phy_enable()
720 	value = pads_readl(pcie, PADS_CTL);  in tegra_pcie_phy_enable()
722 	pads_writel(pcie, value, PADS_CTL);  in tegra_pcie_phy_enable()
728 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)  argument
730 	const struct tegra_pcie_soc *soc = pcie->soc;
738 	if (pcie->phy) {
740 		value = afi_readl(pcie, AFI_PLLE_CONTROL);
743 		afi_writel(pcie, value, AFI_PLLE_CONTROL);
747 		afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
749 	value = afi_readl(pcie, AFI_PCIE_CONFIG);
751 	value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
753 	list_for_each_entry(port, &pcie->ports, list)
756 	afi_writel(pcie, value, AFI_PCIE_CONFIG);
758 	value = afi_readl(pcie, AFI_FUSE);
765 	afi_writel(pcie, value, AFI_FUSE);
768 	if (pcie->phy)
769 		err = tegra_xusb_phy_enable(pcie->phy);
771 		err = tegra_pcie_phy_enable(pcie);
781 	err = reset_deassert(&pcie->reset_pcie_x);
790 	/* finally enable PCIe */
791 	value = afi_readl(pcie, AFI_CONFIGURATION);
793 	afi_writel(pcie, value, AFI_CONFIGURATION);
796 	afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
797 	afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
798 	afi_writel(pcie, 0, AFI_INTR_MASK);
799 	afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
806 	struct tegra_pcie *pcie = dev_get_priv(bus);  local
813 	size = resource_size(&pcie->cs);
814 	axi = pcie->cs.start;
816 	afi_writel(pcie, axi, AFI_AXI_BAR0_START);
817 	afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
818 	afi_writel(pcie, fpci, AFI_FPCI_BAR0);
829 	afi_writel(pcie, axi, AFI_AXI_BAR1_START);
830 	afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
831 	afi_writel(pcie, fpci, AFI_FPCI_BAR1);
838 	afi_writel(pcie, axi, AFI_AXI_BAR2_START);
839 	afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
840 	afi_writel(pcie, fpci, AFI_FPCI_BAR2);
847 	afi_writel(pcie, axi, AFI_AXI_BAR3_START);
848 	afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
849 	afi_writel(pcie, fpci, AFI_FPCI_BAR3);
852 	afi_writel(pcie, 0, AFI_AXI_BAR4_START);
853 	afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
854 	afi_writel(pcie, 0, AFI_FPCI_BAR4);
856 	afi_writel(pcie, 0, AFI_AXI_BAR5_START);
857 	afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
858 	afi_writel(pcie, 0, AFI_FPCI_BAR5);
861 	afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
862 	afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
863 	afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
864 	afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
867 	afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
868 	afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
869 	afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
870 	afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
889 		ret = port->pcie->soc->afi_pex2_ctrl;
902 	value = afi_readl(port->pcie, ctrl);
904 	afi_writel(port->pcie, value, ctrl);
908 	value = afi_readl(port->pcie, ctrl);
910 	afi_writel(port->pcie, value, ctrl);
915 	struct tegra_pcie *pcie = port->pcie;  local
916 	const struct tegra_pcie_soc *soc = pcie->soc;
921 	value = afi_readl(pcie, ctrl);
924 	if (pcie->soc->has_pex_clkreq_en)
929 	afi_writel(pcie, value, ctrl);
940 	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
942 		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
994 	value = afi_readl(port->pcie, ctrl);
996 	afi_writel(port->pcie, value, ctrl);
999 	value = afi_readl(port->pcie, ctrl);
1001 	afi_writel(port->pcie, value, ctrl);
1010 static int tegra_pcie_enable(struct tegra_pcie *pcie)  argument
1014 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1089 	struct tegra_pcie *pcie = dev_get_priv(dev);  local
1093 	pcie->soc = &pci_tegra_soc[id];
1095 	INIT_LIST_HEAD(&pcie->ports);
1097 	if (tegra_pcie_parse_dt(dev, id, pcie))
1105 	struct tegra_pcie *pcie = dev_get_priv(dev);  local
1109 	err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
1115 	err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
1121 	err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
1127 	err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
1133 	err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
1139 	err = power_domain_get(dev, &pcie->pwrdom);
1146 	err = tegra_pcie_power_on(pcie);
1152 	err = tegra_pcie_enable_controller(pcie);
1164 	err = tegra_pcie_enable(pcie);
1166 		pr_err("failed to enable PCIe");
1179 	{ .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1180 	{ .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1181 	{ .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1182 	{ .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1183 	{ .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },