16 #define SH7751_BCR1	(vu_long *)0xFF800000
17 #define SH7751_BCR2	(vu_short *)0xFF800004
18 #define SH7751_WCR1	(vu_long *)0xFF800008
19 #define SH7751_WCR2	(vu_long *)0xFF80000C
20 #define SH7751_WCR3	(vu_long *)0xFF800010
21 #define SH7751_MCR	(vu_long *)0xFF800014
22 #define SH7751_BCR3	(vu_short *)0xFF800050
23 #define SH7751_PCICONF0 (vu_long *)0xFE200000
24 #define SH7751_PCICONF1 (vu_long *)0xFE200004
25 #define SH7751_PCICONF2 (vu_long *)0xFE200008
26 #define SH7751_PCICONF3 (vu_long *)0xFE20000C
27 #define SH7751_PCICONF4 (vu_long *)0xFE200010
28 #define SH7751_PCICONF5 (vu_long *)0xFE200014
29 #define SH7751_PCICONF6 (vu_long *)0xFE200018
30 #define SH7751_PCICR    (vu_long *)0xFE200100
31 #define SH7751_PCILSR0  (vu_long *)0xFE200104
32 #define SH7751_PCILSR1  (vu_long *)0xFE200108
33 #define SH7751_PCILAR0  (vu_long *)0xFE20010C
34 #define SH7751_PCILAR1  (vu_long *)0xFE200110
35 #define SH7751_PCIMBR   (vu_long *)0xFE2001C4
36 #define SH7751_PCIIOBR  (vu_long *)0xFE2001C8
37 #define SH7751_PCIPINT  (vu_long *)0xFE2001CC
38 #define SH7751_PCIPINTM (vu_long *)0xFE2001D0
39 #define SH7751_PCICLKR  (vu_long *)0xFE2001D4
40 #define SH7751_PCIBCR1  (vu_long *)0xFE2001E0
41 #define SH7751_PCIBCR2  (vu_long *)0xFE2001E4
42 #define SH7751_PCIWCR1  (vu_long *)0xFE2001E8
43 #define SH7751_PCIWCR2  (vu_long *)0xFE2001EC
44 #define SH7751_PCIWCR3  (vu_long *)0xFE2001F0
45 #define SH7751_PCIMCR   (vu_long *)0xFE2001F4
46 #define SH7751_PCIBCR3  (vu_long *)0xFE2001F8
48 #define BCR1_BREQEN				0x00080000
49 #define PCI_SH7751_ID			0x35051054
50 #define PCI_SH7751R_ID			0x350E1054
51 #define SH7751_PCICONF1_WCC		0x00000080
52 #define SH7751_PCICONF1_PER		0x00000040
53 #define SH7751_PCICONF1_BUM		0x00000004
54 #define SH7751_PCICONF1_MES		0x00000002
55 #define SH7751_PCICONF1_CMDS	0x000000C6
56 #define SH7751_PCI_HOST_BRIDGE	0x6
57 #define SH7751_PCICR_PREFIX		0xa5000000
58 #define SH7751_PCICR_PRST		0x00000002
59 #define SH7751_PCICR_CFIN		0x00000001
60 #define SH7751_PCIPINT_D3		0x00000002
61 #define SH7751_PCIPINT_D0		0x00000001
62 #define SH7751_PCICLKR_PREFIX   0xa5000000
64 #define SH7751_PCI_MEM_BASE		0xFD000000
65 #define SH7751_PCI_MEM_SIZE		0x01000000
66 #define SH7751_PCI_IO_BASE		0xFE240000
67 #define SH7751_PCI_IO_SIZE		0x00040000
69 #define SH7751_PCIPAR   (vu_long *)0xFE2001C0
70 #define SH7751_PCIPDR   (vu_long *)0xFE200220
79 	u32 par_data = 0x80000000 | dev;  in pci_sh4_read_config_dword()
81 	p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);  in pci_sh4_read_config_dword()
84 	return 0;  in pci_sh4_read_config_dword()
90 	u32 par_data = 0x80000000 | dev;  in pci_sh4_write_config_dword()
92 	p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);  in pci_sh4_write_config_dword()
95 	return 0;  in pci_sh4_write_config_dword()
110 	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {  in pci_sh7751_init()
111 		printf("SH7751_BCR1 value is wrong(0x%08X)\n",  in pci_sh7751_init()
115 	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {  in pci_sh7751_init()
116 		printf("SH7751_BCR2 value is wrong(0x%08X)\n",  in pci_sh7751_init()
120 	if (p4_in(SH7751_BCR2) & 0x01) {  in pci_sh7751_init()
121 		printf("SH7751_BCR2 value is wrong(0x%08X)\n",  in pci_sh7751_init()
136 	p4_out(0xfb900047, SH7751_PCICONF1);	/* K.Kino */  in pci_sh7751_init()
142 	p4_out(0, SH7751_PCICLKR);  in pci_sh7751_init()
143 	p4_out(0x03, SH7751_PCICLKR);  in pci_sh7751_init()
147 	p4_out(0, SH7751_PCIPINTM);  in pci_sh7751_init()
149 	p4_out(0xab000001, SH7751_PCICONF4);  in pci_sh7751_init()
153 	p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);  in pci_sh7751_init()
154 	p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);  in pci_sh7751_init()
155 	p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);  in pci_sh7751_init()
157 	p4_out(0, SH7751_PCILSR1);  in pci_sh7751_init()
158 	p4_out(0, SH7751_PCILAR1);  in pci_sh7751_init()
159 	p4_out(0xd0000000, SH7751_PCICONF6);  in pci_sh7751_init()
168 	p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);  in pci_sh7751_init()
184 	return 0;  in pci_sh7751_init()