Lines Matching full:pcie
2 * PCIe driver for Marvell MVEBU SoCs
23 /* PCIe unit register offsets */
84 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
107 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, in mvebu_get_port_lane() argument
115 pcie->port = port[pex_idx]; in mvebu_get_port_lane()
116 pcie->lane = lane[pex_idx]; in mvebu_get_port_lane()
142 static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, in mvebu_get_port_lane() argument
152 pcie->port = port[pex_idx]; in mvebu_get_port_lane()
153 pcie->lane = lane[pex_idx]; in mvebu_get_port_lane()
167 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) in mvebu_pcie_link_up() argument
170 val = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_link_up()
174 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) in mvebu_pcie_set_local_bus_nr() argument
178 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
181 writel(stat, pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
184 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno) in mvebu_pcie_set_local_dev_nr() argument
188 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_dev_nr()
191 writel(stat, pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_dev_nr()
194 static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie) in mvebu_pcie_get_local_bus_nr() argument
198 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_get_local_bus_nr()
202 static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie) in mvebu_pcie_get_local_dev_nr() argument
206 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_get_local_dev_nr()
218 struct mvebu_pcie *pcie = hose_to_pcie(hose); in mvebu_pcie_read_config_dword() local
219 int local_bus = PCI_BUS(pcie->dev); in mvebu_pcie_read_config_dword()
220 int local_dev = PCI_DEV(pcie->dev); in mvebu_pcie_read_config_dword()
244 writel(reg, pcie->base + PCIE_CONF_ADDR_OFF); in mvebu_pcie_read_config_dword()
245 *val = readl(pcie->base + PCIE_CONF_DATA_OFF); in mvebu_pcie_read_config_dword()
253 struct mvebu_pcie *pcie = hose_to_pcie(hose); in mvebu_pcie_write_config_dword() local
254 int local_bus = PCI_BUS(pcie->dev); in mvebu_pcie_write_config_dword()
255 int local_dev = PCI_DEV(pcie->dev); in mvebu_pcie_write_config_dword()
274 writel(PCIE_CONF_ADDR(dev, offset), pcie->base + PCIE_CONF_ADDR_OFF); in mvebu_pcie_write_config_dword()
275 writel(val, pcie->base + PCIE_CONF_DATA_OFF); in mvebu_pcie_write_config_dword()
281 * Setup PCIE BARs and Address Decode Wins:
285 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) in mvebu_pcie_setup_wins() argument
293 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i)); in mvebu_pcie_setup_wins()
294 writel(0, pcie->base + PCIE_BAR_LO_OFF(i)); in mvebu_pcie_setup_wins()
295 writel(0, pcie->base + PCIE_BAR_HI_OFF(i)); in mvebu_pcie_setup_wins()
299 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i)); in mvebu_pcie_setup_wins()
300 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i)); in mvebu_pcie_setup_wins()
301 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i)); in mvebu_pcie_setup_wins()
304 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF); in mvebu_pcie_setup_wins()
305 writel(0, pcie->base + PCIE_WIN5_BASE_OFF); in mvebu_pcie_setup_wins()
306 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF); in mvebu_pcie_setup_wins()
314 pcie->base + PCIE_WIN04_BASE_OFF(i)); in mvebu_pcie_setup_wins()
315 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i)); in mvebu_pcie_setup_wins()
319 pcie->base + PCIE_WIN04_CTRL_OFF(i)); in mvebu_pcie_setup_wins()
329 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1)); in mvebu_pcie_setup_wins()
330 writel(0, pcie->base + PCIE_BAR_HI_OFF(1)); in mvebu_pcie_setup_wins()
332 pcie->base + PCIE_BAR_CTRL_OFF(1)); in mvebu_pcie_setup_wins()
348 struct mvebu_pcie *pcie = &pcie_bus[i]; in pci_init_board() local
349 struct pci_controller *hose = &pcie->hose; in pci_init_board()
352 mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr); in pci_init_board()
355 if (SELECT(soc_ctrl, pcie->port) == 0) { in pci_init_board()
356 if (pcie->lane == 0) in pci_init_board()
357 debug("%s: skipping port %d\n", __func__, pcie->port); in pci_init_board()
361 pcie->base = (void __iomem *)PCIE_BASE(i); in pci_init_board()
364 if (!mvebu_pcie_link_up(pcie)) { in pci_init_board()
365 debug("%s: PCIe %d.%d - down\n", __func__, in pci_init_board()
366 pcie->port, pcie->lane); in pci_init_board()
369 debug("%s: PCIe %d.%d - up, base %08x\n", __func__, in pci_init_board()
370 pcie->port, pcie->lane, (u32)pcie->base); in pci_init_board()
374 readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie), in pci_init_board()
375 mvebu_pcie_get_local_dev_nr(pcie)); in pci_init_board()
377 mvebu_pcie_set_local_bus_nr(pcie, bus); in pci_init_board()
378 mvebu_pcie_set_local_dev_nr(pcie, 0); in pci_init_board()
379 pcie->dev = PCI_BDF(bus, 0, 0); in pci_init_board()
381 pcie->mem.start = (u32)mvebu_pcie_membase; in pci_init_board()
382 pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1; in pci_init_board()
386 (phys_addr_t)pcie->mem.start, in pci_init_board()
388 printf("PCIe unable to add mbus window for mem at %08x+%08x\n", in pci_init_board()
389 (u32)pcie->mem.start, PCIE_MEM_SIZE); in pci_init_board()
393 mvebu_pcie_setup_wins(pcie); in pci_init_board()
396 reg = readl(pcie->base + PCIE_CMD_OFF); in pci_init_board()
400 writel(reg, pcie->base + PCIE_CMD_OFF); in pci_init_board()
407 pci_set_region(hose->regions + 0, pcie->mem.start, in pci_init_board()
408 pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM); in pci_init_board()
427 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); in pci_init_board()
428 writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); in pci_init_board()