Lines Matching +full:0 +full:x40020000
33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
57 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
59 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
60 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
62 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
72 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
95 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
97 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
104 * 0x1000: 10Mbps full duplex support
105 * 0x0800: 10Mbps half duplex support
106 * 0x0008: Auto-negotiation support
108 #define PHY_DETECT_MASK 0x1808
111 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
112 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
113 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
122 u32 nwctrl; /* 0x0 - Network Control reg */
123 u32 nwcfg; /* 0x4 - Network Config reg */
124 u32 nwsr; /* 0x8 - Network Status reg */
126 u32 dmacr; /* 0x10 - DMA Control reg */
127 u32 txsr; /* 0x14 - TX Status reg */
128 u32 rxqbase; /* 0x18 - RX Q Base address reg */
129 u32 txqbase; /* 0x1c - TX Q Base address reg */
130 u32 rxsr; /* 0x20 - RX Status reg */
132 u32 idr; /* 0x2c - Interrupt Disable reg */
134 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
136 u32 hashl; /* 0x80 - Hash Low address reg */
137 u32 hashh; /* 0x84 - Hash High address reg */
138 #define LADDR_LOW 0
140 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
141 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
144 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
148 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
150 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
163 #define BD_SPACE 0x100000
170 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
215 return 0; in phy_setup_op()
227 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, in phyread()
236 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, in phywrite()
251 if ((phyreg != 0xFFFF) && in phy_detection()
256 return 0; in phy_detection()
267 for (i = 31; i >= 0; i--) { in phy_detection()
269 if ((phyreg != 0xFFFF) && in phy_detection()
274 return 0; in phy_detection()
289 /* Set the MAC bits [31:0] in BOT */ in zynq_gem_setup_mac()
290 macaddrlow = pdata->enetaddr[0]; in zynq_gem_setup_mac()
299 for (i = 0; i < 4; i++) { in zynq_gem_setup_mac()
300 writel(0, ®s->laddr[i][LADDR_LOW]); in zynq_gem_setup_mac()
301 writel(0, ®s->laddr[i][LADDR_HIGH]); in zynq_gem_setup_mac()
303 writel(0, ®s->match[i]); in zynq_gem_setup_mac()
306 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); in zynq_gem_setup_mac()
307 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); in zynq_gem_setup_mac()
309 return 0; in zynq_gem_setup_mac()
344 if (priv->phy_of_handle > 0) in zynq_phy_init()
354 unsigned long clk_rate = 0; in zynq_gem_init()
362 writel(0xFFFFFFFF, ®s->idr); in zynq_gem_init()
365 writel(0, ®s->nwctrl); in zynq_gem_init()
366 writel(0, ®s->txsr); in zynq_gem_init()
367 writel(0, ®s->rxsr); in zynq_gem_init()
368 writel(0, ®s->phymntnc); in zynq_gem_init()
373 writel(0x0, ®s->hashl); in zynq_gem_init()
375 writel(0x0, ®s->hashh); in zynq_gem_init()
378 for (i = 0; i < STAT_SIZE; i++) in zynq_gem_init()
382 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); in zynq_gem_init()
384 for (i = 0; i < RX_BUF; i++) { in zynq_gem_init()
385 priv->rx_bd[i].status = 0xF0000000; in zynq_gem_init()
402 dummy_tx_bd->addr = 0; in zynq_gem_init()
409 dummy_rx_bd->status = 0; in zynq_gem_init()
468 return 0; in zynq_gem_init()
479 memset(priv->tx_bd, 0, sizeof(struct emac_bd)); in zynq_gem_send()
485 current_bd->addr = 0x0; in zynq_gem_send()
515 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
555 current_bd->status = 0xF0000000; /* FIXME */ in zynq_gem_free_pkt()
561 first_bd->status = 0xF0000000; in zynq_gem_free_pkt()
565 priv->rxbd_current = 0; in zynq_gem_free_pkt()
567 return 0; in zynq_gem_free_pkt()
576 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); in zynq_gem_halt()
602 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); in zynq_gem_miiphy_read()
611 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); in zynq_gem_miiphy_write()
623 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); in zynq_gem_probe()
635 if (ret < 0) { in zynq_gem_probe()
660 return 0; in zynq_gem_remove()
687 if (priv->phy_of_handle > 0) in zynq_gem_ofdata_to_platdata()
703 return 0; in zynq_gem_ofdata_to_platdata()