Lines Matching defs:zynq_gem_regs

121 struct zynq_gem_regs {  struct
122 	u32 nwctrl; /* 0x0 - Network Control reg */
123 	u32 nwcfg; /* 0x4 - Network Config reg */
124 	u32 nwsr; /* 0x8 - Network Status reg */
125 	u32 reserved1;
126 	u32 dmacr; /* 0x10 - DMA Control reg */
127 	u32 txsr; /* 0x14 - TX Status reg */
128 	u32 rxqbase; /* 0x18 - RX Q Base address reg */
129 	u32 txqbase; /* 0x1c - TX Q Base address reg */
130 	u32 rxsr; /* 0x20 - RX Status reg */
131 	u32 reserved2[2];
132 	u32 idr; /* 0x2c - Interrupt Disable reg */
133 	u32 reserved3;
134 	u32 phymntnc; /* 0x34 - Phy Maintaince reg */
135 	u32 reserved4[18];
136 	u32 hashl; /* 0x80 - Hash Low address reg */
137 	u32 hashh; /* 0x84 - Hash High address reg */
140 	u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
141 	u32 match[4]; /* 0xa8 - Type ID1 Match reg */
142 	u32 reserved6[18];
144 	u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
145 	u32 reserved9[20];
146 	u32 pcscntrl;
147 	u32 reserved7[143];
148 	u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
149 	u32 reserved8[15];
150 	u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */