Lines Matching +full:inter +full:- +full:data

2  * Xilinx xps_ll_temac ethernet driver for u-boot
6  * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
7  * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
8  * Copyright (C) 2008 - 2011 PetaLogix
10  * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
14  * SPDX-License-Identifier:	GPL-2.0+
48 	u32 ifgp;	/* Transmit Inter Frame Gap Adjustment */
55 	u32 msw;	/* Most Significant Word Data */
56 	u32 lsw;	/* Least Significant Word Data */
86 /* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */
90 /* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */
100 /* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */
109 /* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */
113 /* LSW Data Register for PHY addresses (lsw), [1] p66 */
119 /* LSW Data Register for PHY data (lsw), [1] p66 */
138 /* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */
181 /* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */
241  * fMDC = -------------------   --------->   MC_CLKDIV = -------- - 1
244 #define MC_CLKDIV(f, m)		((f / (2 * m)) - 1)
250 /* Unicast Address Word 0, 1 Registers (UAW0, UAW1), [1] p58-59 */
268 /* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */
277 /* MII Management Write Data Registers (MIIMWD), [1] p66 */