Lines Matching refs:outl
82 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
84 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
86 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
345 outl(ULI526X_RESET, db->ioaddr + DCR0); in uli526x_disable()
352 outl(0, dev->iobase + DCR7); /* Disable Interrupt */ in uli526x_disable()
353 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5); in uli526x_disable()
373 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */ in uli526x_init()
375 outl(db->cr0_data, db->ioaddr + DCR0); in uli526x_init()
424 outl(db->cr7_data, db->ioaddr + DCR7); in uli526x_init()
427 outl(db->cr15_data, db->ioaddr + DCR15); in uli526x_init()
459 outl(0, dev->iobase + DCR7); in uli526x_start_xmit()
473 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */ in uli526x_start_xmit()
478 outl(db->cr5_data, db->ioaddr + DCR5); in uli526x_start_xmit()
485 outl(db->cr7_data, dev->iobase + DCR7); in uli526x_start_xmit()
637 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ in uli526x_descriptor_init()
645 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ in uli526x_descriptor_init()
696 outl(cr6_data, ioaddr + DCR6); in update_cr6()
739 outl(CR9_SROM_READ, cr9_ioaddr); in read_srom_word()
740 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); in read_srom_word()
753 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); in read_srom_word()
756 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); in read_srom_word()
760 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); in read_srom_word()
764 outl(CR9_SROM_READ, cr9_ioaddr); in read_srom_word()
915 outl(cr10_value, ioaddr); in phy_readby_cr10()
934 outl(cr10_value, ioaddr); in phy_writeby_cr10()
943 outl(phy_data , ioaddr); /* MII Clock Low */ in phy_write_1bit()
945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ in phy_write_1bit()
947 outl(phy_data , ioaddr); /* MII Clock Low */ in phy_write_1bit()
959 outl(0x50000 , ioaddr); in phy_read_1bit()
962 outl(0x40000 , ioaddr); in phy_read_1bit()
977 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */ in set_mac_addr()
979 outl(0x1c0, db->ioaddr + DCR13); in set_mac_addr()
980 outl(0, db->ioaddr + DCR14); /* Clear reset port */ in set_mac_addr()
981 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */ in set_mac_addr()
982 outl(0, db->ioaddr + DCR14); /* Clear reset port */ in set_mac_addr()
983 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ in set_mac_addr()
985 outl(0x1b0, db->ioaddr + DCR13); in set_mac_addr()
989 outl(addr, db->ioaddr + DCR14); in set_mac_addr()
992 outl(0, db->ioaddr + DCR13); /* Clear CR13 */ in set_mac_addr()
993 outl(0, db->ioaddr + DCR0); /* Clear CR0 */ in set_mac_addr()