Lines Matching refs:base
45 #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) argument
47 #define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) argument
62 #define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) argument
73 #define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) argument
75 #define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) argument
81 #define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) argument
85 #define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) argument
86 #define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) argument
87 #define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) argument
89 #define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) argument
94 #define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) argument
98 #define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) argument
99 #define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) argument
101 #define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) argument
114 #define reg_TX_CONFIG(base) __REG32(base, 0x00000220) argument
120 #define reg_TX_CONTROL(base) __REG32(base, 0x00000224) argument
127 #define reg_TX_STATUS(base) __REG32(base, 0x00000228) argument
134 #define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) argument
140 #define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) argument
142 #define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270) argument
147 #define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) argument
149 #define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) argument
172 #define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) argument
184 #define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) argument
199 #define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) argument
201 #define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) argument
204 #define reg_RX_CONFIG(base) __REG32(base, 0x00000320) argument
217 #define reg_RX_CONTROL(base) __REG32(base, 0x00000324) argument
224 #define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) argument
232 #define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) argument
234 #define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) argument
239 #define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) argument
241 #define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) argument
252 #define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) argument
258 #define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) argument
260 #define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) argument
423 static unsigned int read_phy (unsigned int base,
425 static void write_phy (unsigned int base,
445 #define dump_phy_regs(base) do{}while(0) argument
452 static void tx_diag_regs (unsigned int base) in tx_diag_regs() argument
458 reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI; in tx_diag_regs()
460 dummy = reg_TX_DIAGNOSTIC_DATA(base); in tx_diag_regs()
463 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); in tx_diag_regs()
465 reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI; in tx_diag_regs()
467 dummy = reg_TX_DIAGNOSTIC_DATA(base); in tx_diag_regs()
470 printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); in tx_diag_regs()
476 #define tx_diag_regs(base) do{}while(0) argument
483 static void rx_diag_regs (unsigned int base) in rx_diag_regs() argument
489 reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI; in rx_diag_regs()
491 dummy = reg_RX_DIAGNOSTIC_DATA(base); in rx_diag_regs()
494 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); in rx_diag_regs()
496 reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI; in rx_diag_regs()
498 dummy = reg_RX_DIAGNOSTIC_DATA(base); in rx_diag_regs()
501 printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); in rx_diag_regs()
507 #define rx_diag_regs(base) do{}while(0) argument
514 static void debug_mii_regs (unsigned int base) in debug_mii_regs() argument
516 printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); in debug_mii_regs()
517 printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); in debug_mii_regs()
518 printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); in debug_mii_regs()
519 printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); in debug_mii_regs()
520 printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); in debug_mii_regs()
521 printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); in debug_mii_regs()
526 #define debug_mii_regs(base) do{}while(0) argument
532 static void phy_wait (unsigned int base, unsigned int condition) in phy_wait() argument
537 while (reg_MII_MGMT_INDICATORS(base) & condition) { in phy_wait()
550 static unsigned int read_phy (unsigned int base, in read_phy() argument
555 phy_wait (base, MII_MGMT_INDICATORS_BUSY); in read_phy()
557 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; in read_phy()
560 reg_MII_MGMT_COMMAND(base) = 0; in read_phy()
563 reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE; in read_phy()
566 phy_wait (base, in read_phy()
569 value = reg_MII_MGMT_STATUS(base); in read_phy()
571 reg_MII_MGMT_COMMAND(base) = 0; in read_phy()
579 static void write_phy (unsigned int base, in write_phy() argument
583 phy_wait (base, MII_MGMT_INDICATORS_BUSY); in write_phy()
585 reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; in write_phy()
588 reg_MII_MGMT_COMMAND(base) = 0; in write_phy()
591 reg_MII_MGMT_CONTROL(base) = phy_data; in write_phy()
600 unsigned long base; in marvell_88e_phy_config() local
612 base = dev->iobase; in marvell_88e_phy_config()
631 write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | in marvell_88e_phy_config()
670 write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); in marvell_88e_phy_config()
671 write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); in marvell_88e_phy_config()
741 unsigned long base; in tsi108_eth_probe() local
749 base = dev->iobase; in tsi108_eth_probe()
751 reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT; in tsi108_eth_probe()
754 reg_TX_CONFIG(base) = 0x00000000; in tsi108_eth_probe()
755 reg_RX_CONFIG(base) = 0x00000000; in tsi108_eth_probe()
757 reg_TX_THRESHOLDS(base) = (192 << 16) | 192; in tsi108_eth_probe()
758 reg_RX_THRESHOLDS(base) = (192 << 16) | 112; in tsi108_eth_probe()
761 reg_MAC_CONFIG_1(base) = 0x00000000; in tsi108_eth_probe()
764 reg_MAC_CONFIG_1(base) = in tsi108_eth_probe()
767 reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE; in tsi108_eth_probe()
768 reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE; in tsi108_eth_probe()
772 reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) | in tsi108_eth_probe()
776 reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | in tsi108_eth_probe()
789 reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; in tsi108_eth_probe()
793 reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; in tsi108_eth_probe()
795 reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; in tsi108_eth_probe()
796 reg_MAC_CONFIG_2(base) = value; in tsi108_eth_probe()
798 reg_RX_CONFIG(base) = RX_CONFIG_SE; in tsi108_eth_probe()
799 reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; in tsi108_eth_probe()
800 reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; in tsi108_eth_probe()
830 reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01; in tsi108_eth_probe()
831 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current; in tsi108_eth_probe()
833 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; in tsi108_eth_probe()
835 reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; in tsi108_eth_probe()
836 reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; in tsi108_eth_probe()
850 reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; in tsi108_eth_probe()
860 unsigned long base; in tsi108_eth_send() local
865 base = dev->iobase; in tsi108_eth_send()
879 tx_diag_regs(base); in tsi108_eth_send()
918 reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr; in tsi108_eth_send()
919 reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID; in tsi108_eth_send()
930 unsigned long base; in tsi108_eth_recv() local
935 base = dev->iobase; in tsi108_eth_recv()
991 if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) { in tsi108_eth_recv()
993 reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0; in tsi108_eth_recv()
994 reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0]; in tsi108_eth_recv()
995 reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; in tsi108_eth_recv()
1006 unsigned long base; in tsi108_eth_halt() local
1008 base = dev->iobase; in tsi108_eth_halt()
1011 reg_TX_CONFIG(base) = TX_CONFIG_RST; in tsi108_eth_halt()
1012 reg_RX_CONFIG(base) = RX_CONFIG_RST; in tsi108_eth_halt()
1015 reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET; in tsi108_eth_halt()