45 #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset))))  argument
47 #define reg_MAC_CONFIG_1(base)		__REG32(base, 0x00000000)  argument
62 #define reg_MAC_CONFIG_2(base)		__REG32(base, 0x00000004)  argument
73 #define reg_MAXIMUM_FRAME_LENGTH(base)		__REG32(base, 0x00000010)  argument
75 #define reg_MII_MGMT_CONFIG(base)		__REG32(base, 0x00000020)  argument
81 #define reg_MII_MGMT_COMMAND(base)		__REG32(base, 0x00000024)  argument
85 #define reg_MII_MGMT_ADDRESS(base)		__REG32(base, 0x00000028)  argument
86 #define reg_MII_MGMT_CONTROL(base)		__REG32(base, 0x0000002c)  argument
87 #define reg_MII_MGMT_STATUS(base)		__REG32(base, 0x00000030)  argument
89 #define reg_MII_MGMT_INDICATORS(base)		__REG32(base, 0x00000034)  argument
94 #define reg_INTERFACE_STATUS(base)		__REG32(base, 0x0000003c)  argument
98 #define reg_STATION_ADDRESS_1(base)		__REG32(base, 0x00000040)  argument
99 #define reg_STATION_ADDRESS_2(base)		__REG32(base, 0x00000044)  argument
101 #define reg_PORT_CONTROL(base)			__REG32(base, 0x00000200)  argument
114 #define reg_TX_CONFIG(base)		__REG32(base, 0x00000220)  argument
120 #define reg_TX_CONTROL(base)		__REG32(base, 0x00000224)  argument
127 #define reg_TX_STATUS(base)		__REG32(base, 0x00000228)  argument
134 #define reg_TX_EXTENDED_STATUS(base)		__REG32(base, 0x0000022c)  argument
140 #define reg_TX_THRESHOLDS(base)			__REG32(base, 0x00000230)  argument
142 #define reg_TX_DIAGNOSTIC_ADDR(base)           __REG32(base, 0x00000270)  argument
147 #define reg_TX_DIAGNOSTIC_DATA(base)		__REG32(base, 0x00000274)  argument
149 #define reg_TX_ERROR_STATUS(base)		__REG32(base, 0x00000278)  argument
172 #define reg_TX_QUEUE_0_CONFIG(base)		__REG32(base, 0x00000280)  argument
184 #define reg_TX_QUEUE_0_BUF_CONFIG(base)		__REG32(base, 0x00000284)  argument
199 #define reg_TX_QUEUE_0_PTR_LOW(base)		__REG32(base, 0x00000288)  argument
201 #define reg_TX_QUEUE_0_PTR_HIGH(base)		__REG32(base, 0x0000028c)  argument
204 #define reg_RX_CONFIG(base)			__REG32(base, 0x00000320)  argument
217 #define reg_RX_CONTROL(base)			__REG32(base, 0x00000324)  argument
224 #define reg_RX_EXTENDED_STATUS(base)		__REG32(base, 0x0000032c)  argument
232 #define reg_RX_THRESHOLDS(base)			__REG32(base, 0x00000330)  argument
234 #define reg_RX_DIAGNOSTIC_ADDR(base)		__REG32(base, 0x00000370)  argument
239 #define reg_RX_DIAGNOSTIC_DATA(base)		__REG32(base, 0x00000374)  argument
241 #define reg_RX_QUEUE_0_CONFIG(base)		__REG32(base, 0x00000380)  argument
252 #define reg_RX_QUEUE_0_BUF_CONFIG(base)		__REG32(base, 0x00000384)  argument
258 #define reg_RX_QUEUE_0_PTR_LOW(base)		__REG32(base, 0x00000388)  argument
260 #define reg_RX_QUEUE_0_PTR_HIGH(base)		__REG32(base, 0x0000038c)  argument
445 #define dump_phy_regs(base) do{}while(0)  argument
452 static void tx_diag_regs (unsigned int base)  in tx_diag_regs()
476 #define tx_diag_regs(base) do{}while(0)  argument
483 static void rx_diag_regs (unsigned int base)  in rx_diag_regs()
507 #define rx_diag_regs(base) do{}while(0)  argument
514 static void debug_mii_regs (unsigned int base)  in debug_mii_regs()
526 #define debug_mii_regs(base) do{}while(0)  argument
532 static void phy_wait (unsigned int base, unsigned int condition)  in phy_wait()
550 static unsigned int read_phy (unsigned int base,  in read_phy()
579 static void write_phy (unsigned int base,  in write_phy()
600 	unsigned long base;  in marvell_88e_phy_config()  local
741 	unsigned long base;  in tsi108_eth_probe()  local
860 	unsigned long base;  in tsi108_eth_send()  local
930 	unsigned long base;  in tsi108_eth_recv()  local
1006 	unsigned long base;  in tsi108_eth_halt()  local