341 	flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +  in rx_descs_init()
346 		desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]  in rx_descs_init()
348 		desc_p->next = (uintptr_t)&desc_table_p[idx + 1];  in rx_descs_init()
354 	desc_p->next = (uintptr_t)&desc_table_p[0];  in rx_descs_init()
356 	flush_dcache_range((uintptr_t)priv->rx_chain,  in rx_descs_init()
357 			   (uintptr_t)priv->rx_chain +  in rx_descs_init()
360 	writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));  in rx_descs_init()
373 		desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]  in tx_descs_init()
375 		desc_p->next = (uintptr_t)&desc_table_p[idx + 1];  in tx_descs_init()
381 	desc_p->next =  (uintptr_t)&desc_table_p[0];  in tx_descs_init()
384 	flush_dcache_range((uintptr_t)priv->tx_chain,  in tx_descs_init()
385 			   (uintptr_t)priv->tx_chain +  in tx_descs_init()
388 	writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);  in tx_descs_init()
504 	uintptr_t desc_start = (uintptr_t)desc_p;  in _sun8i_eth_recv()
505 	uintptr_t desc_end = desc_start +  in _sun8i_eth_recv()
508 	ulong data_start = (uintptr_t)desc_p->buf_addr;  in _sun8i_eth_recv()
550 	uintptr_t desc_start = (uintptr_t)desc_p;  in _sun8i_emac_eth_send()
551 	uintptr_t desc_end = desc_start +  in _sun8i_emac_eth_send()
554 	uintptr_t data_start = (uintptr_t)desc_p->buf_addr;  in _sun8i_emac_eth_send()
555 	uintptr_t data_end = data_start +  in _sun8i_emac_eth_send()
701 	uintptr_t desc_start = (uintptr_t)desc_p;  in _sun8i_free_pkt()
702 	uintptr_t desc_end = desc_start +  in _sun8i_free_pkt()
843 	{.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
845 		.data = (uintptr_t)A64_EMAC },
847 		.data = (uintptr_t)A83T_EMAC },