5  * Copyright (C) 2015-2017  Renesas Electronics Corporation
9  * SPDX-License-Identifier:	GPL-2.0+
13 #include <clk.h>
124 	struct clk		clk;  member
134 	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);  in ravb_invalidate_dcache()
142 	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];  in ravb_send()
145 	/* Update TX descriptor */  in ravb_send()
148 	desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);  in ravb_send()
149 	desc->dptr = (uintptr_t)packet;  in ravb_send()
153 	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))  in ravb_send()
154 		setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);  in ravb_send()
160 		if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)  in ravb_send()
166 		return -ETIMEDOUT;  in ravb_send()
168 	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);  in ravb_send()
175 	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];  in ravb_recv()
181 	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)  in ravb_recv()
182 		return -EAGAIN;  in ravb_recv()
185 	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {  in ravb_recv()
186 		desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;  in ravb_recv()
187 		return -EAGAIN;  in ravb_recv()
190 	len = desc->data.ctrl & RAVB_DESC_DS_MASK;  in ravb_recv()
191 	packet = (u8 *)(uintptr_t)desc->data.dptr;  in ravb_recv()
201 	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];  in ravb_free_pkt()
204 	desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);  in ravb_free_pkt()
208 	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;  in ravb_free_pkt()
209 	desc = &eth->rx_desc[eth->rx_desc_idx];  in ravb_free_pkt()
220 	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);  in ravb_reset()
223 	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,  in ravb_reset()
233 	memset(eth->base_desc, 0x0, desc_size);  in ravb_base_desc_init()
236 		eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;  in ravb_base_desc_init()
238 	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);  in ravb_base_desc_init()
241 	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);  in ravb_base_desc_init()
250 	memset(eth->tx_desc, 0x0, desc_size);  in ravb_tx_desc_init()
251 	eth->tx_desc_idx = 0;  in ravb_tx_desc_init()
254 		eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;  in ravb_tx_desc_init()
257 	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;  in ravb_tx_desc_init()
258 	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;  in ravb_tx_desc_init()
259 	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);  in ravb_tx_desc_init()
261 	/* Point the controller to the TX descriptor list. */  in ravb_tx_desc_init()
262 	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;  in ravb_tx_desc_init()
263 	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;  in ravb_tx_desc_init()
264 	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],  in ravb_tx_desc_init()
274 	memset(eth->rx_desc, 0x0, desc_size);  in ravb_rx_desc_init()
275 	eth->rx_desc_idx = 0;  in ravb_rx_desc_init()
278 		eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |  in ravb_rx_desc_init()
280 		eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;  in ravb_rx_desc_init()
282 		eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;  in ravb_rx_desc_init()
283 		eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];  in ravb_rx_desc_init()
287 	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;  in ravb_rx_desc_init()
288 	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;  in ravb_rx_desc_init()
289 	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);  in ravb_rx_desc_init()
292 	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;  in ravb_rx_desc_init()
293 	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;  in ravb_rx_desc_init()
294 	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],  in ravb_rx_desc_init()
305 	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);  in ravb_phy_config()
307 		return -ENODEV;  in ravb_phy_config()
311 	eth->phydev = phydev;  in ravb_phy_config()
313 	/* 10BASE is not supported for Ethernet AVB MAC */  in ravb_phy_config()
314 	phydev->supported &= ~(SUPPORTED_10baseT_Full  in ravb_phy_config()
316 	if (pdata->max_speed != 1000) {  in ravb_phy_config()
317 		phydev->supported &= ~(SUPPORTED_1000baseT_Half  in ravb_phy_config()
319 		reg = phy_read(phydev, -1, MII_CTRL1000);  in ravb_phy_config()
321 		phy_write(phydev, -1, MII_CTRL1000, reg);  in ravb_phy_config()
329 /* Set Mac address */
334 	unsigned char *mac = pdata->enetaddr;  in ravb_write_hwaddr()  local
336 	writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],  in ravb_write_hwaddr()
337 	       eth->iobase + RAVB_REG_MAHR);  in ravb_write_hwaddr()
339 	writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);  in ravb_write_hwaddr()
344 /* E-MAC init function */
347 	/* Disable MAC Interrupt */  in ravb_mac_init()
348 	writel(0, eth->iobase + RAVB_REG_ECSIPR);  in ravb_mac_init()
351 	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);  in ravb_mac_init()
356 /* AVB-DMAC init function */
369 	writel(0, eth->iobase + RAVB_REG_RIC0);  in ravb_dmac_init()
370 	writel(0, eth->iobase + RAVB_REG_RIC1);  in ravb_dmac_init()
371 	writel(0, eth->iobase + RAVB_REG_RIC2);  in ravb_dmac_init()
372 	writel(0, eth->iobase + RAVB_REG_TIC);  in ravb_dmac_init()
375 	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);  in ravb_dmac_init()
378 	writel(0x18000001, eth->iobase + RAVB_REG_RCR);  in ravb_dmac_init()
381 	writel(0x00222210, eth->iobase + RAVB_REG_TGC);  in ravb_dmac_init()
383 	/* Delay CLK: 2ns */  in ravb_dmac_init()
384 	if (pdata->max_speed == 1000)  in ravb_dmac_init()
385 		writel(BIT(14), eth->iobase + RAVB_REG_APSR);  in ravb_dmac_init()
397 	/* Configure AVB-DMAC register */  in ravb_config()
400 	/* Configure E-MAC registers */  in ravb_config()
409 	phy = eth->phydev;  in ravb_config()
416 	if (phy->speed == 100)  in ravb_config()
417 		writel(0, eth->iobase + RAVB_REG_GECMR);  in ravb_config()
418 	else if (phy->speed == 1000)  in ravb_config()
419 		writel(1, eth->iobase + RAVB_REG_GECMR);  in ravb_config()
422 	if (phy->duplex)  in ravb_config()
425 	writel(mask, eth->iobase + RAVB_REG_ECMR);  in ravb_config()
427 	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);  in ravb_config()
437 	ret = clk_enable(&eth->clk);  in ravb_start()
453 	/* Setting the control will start the AVB-DMAC process. */  in ravb_start()
454 	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);  in ravb_start()
459 	clk_disable(&eth->clk);  in ravb_start()
468 	clk_disable(&eth->clk);  in ravb_stop()
479 	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);  in ravb_probe()
480 	eth->iobase = iobase;  in ravb_probe()
482 	ret = clk_get_by_index(dev, 0, &eth->clk);  in ravb_probe()
488 		ret = -ENOMEM;  in ravb_probe()
492 	mdiodev->read = bb_miiphy_read;  in ravb_probe()
493 	mdiodev->write = bb_miiphy_write;  in ravb_probe()
495 	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);  in ravb_probe()
501 	eth->bus = miiphy_get_dev_by_name(dev->name);  in ravb_probe()
508 	unmap_physmem(eth->iobase, MAP_NOCACHE);  in ravb_probe()
516 	free(eth->phydev);  in ravb_remove()
517 	mdio_unregister(eth->bus);  in ravb_remove()
518 	mdio_free(eth->bus);  in ravb_remove()
519 	unmap_physmem(eth->iobase, MAP_NOCACHE);  in ravb_remove()
531 	struct ravb_priv *eth = bus->priv;  in ravb_bb_mdio_active()
533 	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);  in ravb_bb_mdio_active()
540 	struct ravb_priv *eth = bus->priv;  in ravb_bb_mdio_tristate()
542 	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);  in ravb_bb_mdio_tristate()
549 	struct ravb_priv *eth = bus->priv;  in ravb_bb_set_mdio()
552 		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);  in ravb_bb_set_mdio()
554 		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);  in ravb_bb_set_mdio()
561 	struct ravb_priv *eth = bus->priv;  in ravb_bb_get_mdio()
563 	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;  in ravb_bb_get_mdio()
570 	struct ravb_priv *eth = bus->priv;  in ravb_bb_set_mdc()
573 		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);  in ravb_bb_set_mdc()
575 		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);  in ravb_bb_set_mdc()
617 	pdata->iobase = devfdt_get_addr(dev);  in ravb_ofdata_to_platdata()
618 	pdata->phy_interface = -1;  in ravb_ofdata_to_platdata()
619 	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",  in ravb_ofdata_to_platdata()
622 		pdata->phy_interface = phy_get_interface_by_name(phy_mode);  in ravb_ofdata_to_platdata()
623 	if (pdata->phy_interface == -1) {  in ravb_ofdata_to_platdata()
625 		return -EINVAL;  in ravb_ofdata_to_platdata()
628 	pdata->max_speed = 1000;  in ravb_ofdata_to_platdata()
629 	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);  in ravb_ofdata_to_platdata()
631 		pdata->max_speed = fdt32_to_cpu(*cell);  in ravb_ofdata_to_platdata()
633 	sprintf(bb_miiphy_buses[0].name, dev->name);  in ravb_ofdata_to_platdata()
639 	{ .compatible = "renesas,etheravb-r8a7795" },
640 	{ .compatible = "renesas,etheravb-r8a7796" },
641 	{ .compatible = "renesas,etheravb-rcar-gen3" },