Lines Matching +full:shut +full:- +full:down +full:- +full:gpios
4 * SPDX-License-Identifier: GPL-2.0+
42 if (!dm_gpio_is_valid(&priv->rst_gpio)) in board_netphy_reset()
46 dm_gpio_set_value(&priv->rst_gpio, 0); in board_netphy_reset()
48 dm_gpio_set_value(&priv->rst_gpio, 1); in board_netphy_reset()
57 struct pic32_ectl_regs *ectl_p = priv->ectl_regs; in pic32_mii_init()
58 struct pic32_emac_regs *emac_p = priv->emac_regs; in pic32_mii_init()
64 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
67 wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false, in pic32_mii_init()
71 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
76 writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */ in pic32_mii_init()
78 writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */ in pic32_mii_init()
81 if (priv->phyif == PHY_INTERFACE_MODE_RMII) { in pic32_mii_init()
82 writel(EMAC_RMII_RESET, &emac_p->supp.set); in pic32_mii_init()
84 writel(EMAC_RMII_RESET, &emac_p->supp.clr); in pic32_mii_init()
87 return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii); in pic32_mii_init()
97 priv->phydev = phy_connect(mii, priv->phy_addr, in pic32_phy_init()
98 dev, priv->phyif); in pic32_phy_init()
99 if (!priv->phydev) { in pic32_phy_init()
108 priv->phydev->supported = SUPPORTED_10baseT_Half | in pic32_phy_init()
114 priv->phydev->advertising = ADVERTISED_10baseT_Half | in pic32_phy_init()
120 priv->phydev->autoneg = AUTONEG_ENABLE; in pic32_phy_init()
130 struct phy_device *phydev = priv->phydev; in pic32_mac_adjust_link()
131 struct pic32_emac_regs *emac_p = priv->emac_regs; in pic32_mac_adjust_link()
133 if (!phydev->link) { in pic32_mac_adjust_link()
134 printf("%s: No link.\n", phydev->dev->name); in pic32_mac_adjust_link()
135 return -EINVAL; in pic32_mac_adjust_link()
138 if (phydev->duplex) { in pic32_mac_adjust_link()
139 writel(EMAC_FULLDUP, &emac_p->cfg2.set); in pic32_mac_adjust_link()
140 writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw); in pic32_mac_adjust_link()
142 writel(EMAC_FULLDUP, &emac_p->cfg2.clr); in pic32_mac_adjust_link()
143 writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw); in pic32_mac_adjust_link()
146 switch (phydev->speed) { in pic32_mac_adjust_link()
148 writel(EMAC_RMII_SPD100, &emac_p->supp.set); in pic32_mac_adjust_link()
151 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_adjust_link()
154 printf("%s: Speed was bad\n", phydev->dev->name); in pic32_mac_adjust_link()
155 return -EINVAL; in pic32_mac_adjust_link()
159 phydev->drv->name, phydev->speed, in pic32_mac_adjust_link()
160 (phydev->port == PORT_TP) ? "T" : "X", in pic32_mac_adjust_link()
161 (phydev->duplex) ? "full" : "half"); in pic32_mac_adjust_link()
168 struct pic32_emac_regs *emac_p = priv->emac_regs; in pic32_mac_init()
173 writel(v, &emac_p->cfg1.raw); in pic32_mac_init()
177 writel(v, &emac_p->cfg2.raw); in pic32_mac_init()
179 /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */ in pic32_mac_init()
180 writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw); in pic32_mac_init()
182 /* recommended non-back-to-back interpacket gap is 0xc12 */ in pic32_mac_init()
183 writel(0xc12, &emac_p->ipgr.raw); in pic32_mac_init()
186 writel(0x370f, &emac_p->clrt.raw); in pic32_mac_init()
189 writel(0x600, &emac_p->maxf.raw); in pic32_mac_init()
192 writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw); in pic32_mac_init()
193 writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw); in pic32_mac_init()
194 writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw); in pic32_mac_init()
197 writel(EMAC_RMII_SPD100, &emac_p->supp.clr); in pic32_mac_init()
202 stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR); in pic32_mac_init()
208 printf("MAC: Link is DOWN!\n"); in pic32_mac_init()
216 struct pic32_emac_regs *emac_p = priv->emac_regs; in pic32_mac_reset()
220 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); in pic32_mac_reset()
224 writel(0, &emac_p->cfg1.raw); in pic32_mac_reset()
227 mii = priv->phydev->bus; in pic32_mac_reset()
228 if (mii && mii->reset) in pic32_mac_reset()
229 mii->reset(mii); in pic32_mac_reset()
235 struct pic32_ectl_regs *ectl_p = priv->ectl_regs; in pic32_ctrl_reset()
239 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
242 wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false, in pic32_ctrl_reset()
245 while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT) in pic32_ctrl_reset()
246 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_ctrl_reset()
249 writel(0xffffffff, &ectl_p->irq.clr); in pic32_ctrl_reset()
252 writel(0xffffffff, &ectl_p->txst.clr); in pic32_ctrl_reset()
253 writel(0xffffffff, &ectl_p->rxst.clr); in pic32_ctrl_reset()
256 writel(0x00ff, &ectl_p->rxfc.clr); in pic32_ctrl_reset()
267 writel(v, &ectl_p->rxfc.set); in pic32_ctrl_reset()
270 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_ctrl_reset()
275 struct pic32_ectl_regs *ectl_p = priv->ectl_regs; in pic32_rx_desc_init()
279 priv->rxd_idx = 0; in pic32_rx_desc_init()
281 rxd = &priv->rxd_ring[idx]; in pic32_rx_desc_init()
284 rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY; in pic32_rx_desc_init()
287 rxd->data_buff = virt_to_phys(net_rx_packets[idx]); in pic32_rx_desc_init()
290 rxd->next_ed = virt_to_phys(rxd + 1); in pic32_rx_desc_init()
293 rxd->stat1 = 0; in pic32_rx_desc_init()
294 rxd->stat2 = 0; in pic32_rx_desc_init()
297 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_rx_desc_init()
301 rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]); in pic32_rx_desc_init()
304 flush_dcache_range((ulong)priv->rxd_ring, in pic32_rx_desc_init()
305 (ulong)priv->rxd_ring + sizeof(priv->rxd_ring)); in pic32_rx_desc_init()
307 /* set rx desc-ring start address */ in pic32_rx_desc_init()
308 writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw); in pic32_rx_desc_init()
311 bufsz = readl(&ectl_p->con2.raw); in pic32_rx_desc_init()
314 writel(bufsz, &ectl_p->con2.raw); in pic32_rx_desc_init()
319 writel(ETHCON_RXEN, &ectl_p->con1.set); in pic32_rx_desc_init()
334 phy_config(priv->phydev); in pic32_eth_start()
337 pic32_mac_init(priv, &pdata->enetaddr[0]); in pic32_eth_start()
343 phy_startup(priv->phydev); in pic32_eth_start()
352 struct pic32_ectl_regs *ectl_p = priv->ectl_regs; in pic32_eth_stop()
353 struct pic32_emac_regs *emac_p = priv->emac_regs; in pic32_eth_stop()
356 if (readl(&ectl_p->con1.raw) & ETHCON_ON) in pic32_eth_stop()
357 phy_reset(priv->phydev); in pic32_eth_stop()
359 /* Shut down the PHY */ in pic32_eth_stop()
360 phy_shutdown(priv->phydev); in pic32_eth_stop()
363 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
367 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); in pic32_eth_stop()
370 writel(0, &emac_p->cfg1.raw); in pic32_eth_stop()
374 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
377 /* wait until everything is down */ in pic32_eth_stop()
378 wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false, in pic32_eth_stop()
382 writel(0xffffffff, &ectl_p->irq.clr); in pic32_eth_stop()
388 struct pic32_ectl_regs *ectl_p = priv->ectl_regs; in pic32_eth_send()
392 txd = &priv->txd_ring[0]; in pic32_eth_send()
395 txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length); in pic32_eth_send()
398 txd->data_buff = virt_to_phys(packet); in pic32_eth_send()
401 __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2, in pic32_eth_send()
402 txd->next_ed); in pic32_eth_send()
411 writel(virt_to_phys(txd), &ectl_p->txst.raw); in pic32_eth_send()
414 writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set); in pic32_eth_send()
423 return -ETIMEDOUT; in pic32_eth_send()
426 return -EINTR; in pic32_eth_send()
429 if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) { in pic32_eth_send()
436 if (!(txd->hdr & EDH_EOWN)) in pic32_eth_send()
447 u32 idx = priv->rxd_idx; in pic32_eth_recv()
451 rxd = &priv->rxd_ring[idx]; in pic32_eth_recv()
455 if (rxd->hdr & EDH_EOWN) in pic32_eth_recv()
456 return -EAGAIN; in pic32_eth_recv()
459 if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) { in pic32_eth_recv()
466 __func__, __LINE__, idx, rxd->hdr, in pic32_eth_recv()
467 rxd->data_buff, rxd->stat2, rxd->next_ed); in pic32_eth_recv()
470 if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) { in pic32_eth_recv()
477 rx_count = RSV_RX_COUNT(rxd->stat2); in pic32_eth_recv()
485 return rx_count - 4; in pic32_eth_recv()
491 struct pic32_ectl_regs *ectl_p = priv->ectl_regs; in pic32_eth_free_pkt()
493 int idx = priv->rxd_idx; in pic32_eth_free_pkt()
498 return -EAGAIN; in pic32_eth_free_pkt()
502 rxd = &priv->rxd_ring[idx]; in pic32_eth_free_pkt()
503 rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN; in pic32_eth_free_pkt()
508 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_eth_free_pkt()
511 __func__, __LINE__, idx, rxd->hdr, rxd->data_buff, in pic32_eth_free_pkt()
512 rxd->stat2, rxd->next_ed); in pic32_eth_free_pkt()
514 priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR; in pic32_eth_free_pkt()
536 int phy_addr = -1; in pic32_eth_probe()
538 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg", in pic32_eth_probe()
541 return -EINVAL; in pic32_eth_probe()
544 pdata->iobase = (phys_addr_t)addr; in pic32_eth_probe()
547 pdata->phy_interface = -1; in pic32_eth_probe()
548 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", in pic32_eth_probe()
551 pdata->phy_interface = phy_get_interface_by_name(phy_mode); in pic32_eth_probe()
552 if (pdata->phy_interface == -1) { in pic32_eth_probe()
554 return -EINVAL; in pic32_eth_probe()
558 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), in pic32_eth_probe()
559 "phy-handle"); in pic32_eth_probe()
561 phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); in pic32_eth_probe()
564 gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0, in pic32_eth_probe()
565 &priv->rst_gpio, GPIOD_IS_OUT); in pic32_eth_probe()
567 priv->phyif = pdata->phy_interface; in pic32_eth_probe()
568 priv->phy_addr = phy_addr; in pic32_eth_probe()
569 priv->ectl_regs = iobase; in pic32_eth_probe()
570 priv->emac_regs = iobase + PIC32_EMAC1CFG1; in pic32_eth_probe()
582 dm_gpio_free(dev, &priv->rst_gpio); in pic32_eth_remove()
583 phy_shutdown(priv->phydev); in pic32_eth_remove()
584 free(priv->phydev); in pic32_eth_remove()
588 iounmap(priv->ectl_regs); in pic32_eth_remove()
593 { .compatible = "microchip,pic32mzda-eth" },