Lines Matching full:phydev
108 static int m88e1011s_config(struct phy_device *phydev) in m88e1011s_config() argument
111 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
115 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1011s_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
121 genphy_config_aneg(phydev); in m88e1011s_config()
129 static int m88e1xxx_parse_status(struct phy_device *phydev) in m88e1xxx_parse_status() argument
134 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
145 phydev->link = 0; in m88e1xxx_parse_status()
152 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
159 phydev->link = 1; in m88e1xxx_parse_status()
161 phydev->link = 0; in m88e1xxx_parse_status()
165 phydev->duplex = DUPLEX_FULL; in m88e1xxx_parse_status()
167 phydev->duplex = DUPLEX_HALF; in m88e1xxx_parse_status()
173 phydev->speed = SPEED_1000; in m88e1xxx_parse_status()
176 phydev->speed = SPEED_100; in m88e1xxx_parse_status()
179 phydev->speed = SPEED_10; in m88e1xxx_parse_status()
186 static int m88e1011s_startup(struct phy_device *phydev) in m88e1011s_startup() argument
190 ret = genphy_update_link(phydev); in m88e1011s_startup()
194 return m88e1xxx_parse_status(phydev); in m88e1011s_startup()
198 static int m88e1111s_config(struct phy_device *phydev) in m88e1111s_config() argument
202 if (phy_interface_is_rgmii(phydev)) { in m88e1111s_config()
203 reg = phy_read(phydev, in m88e1111s_config()
205 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || in m88e1111s_config()
206 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { in m88e1111s_config()
208 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in m88e1111s_config()
211 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in m88e1111s_config()
216 phy_write(phydev, in m88e1111s_config()
219 reg = phy_read(phydev, in m88e1111s_config()
229 phy_write(phydev, in m88e1111s_config()
233 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e1111s_config()
234 reg = phy_read(phydev, in m88e1111s_config()
241 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
245 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { in m88e1111s_config()
246 reg = phy_read(phydev, in m88e1111s_config()
249 phy_write(phydev, in m88e1111s_config()
252 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
257 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
261 phy_reset(phydev); in m88e1111s_config()
263 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
269 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
274 phy_reset(phydev); in m88e1111s_config()
276 genphy_config_aneg(phydev); in m88e1111s_config()
277 genphy_restart_aneg(phydev); in m88e1111s_config()
285 void m88e1518_phy_writebits(struct phy_device *phydev, in m88e1518_phy_writebits() argument
295 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); in m88e1518_phy_writebits()
300 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); in m88e1518_phy_writebits()
303 static int m88e1518_config(struct phy_device *phydev) in m88e1518_config() argument
313 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); in m88e1518_config()
314 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); in m88e1518_config()
315 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); in m88e1518_config()
316 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); in m88e1518_config()
317 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); in m88e1518_config()
318 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); in m88e1518_config()
319 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); in m88e1518_config()
320 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); in m88e1518_config()
321 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); in m88e1518_config()
322 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1518_config()
325 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e1518_config()
327 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18); in m88e1518_config()
330 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, in m88e1518_config()
334 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, in m88e1518_config()
338 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); in m88e1518_config()
343 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e1518_config()
344 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1518_config()
351 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1518_config()
355 if (phy_interface_is_rgmii(phydev)) { in m88e1518_config()
356 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); in m88e1518_config()
358 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); in m88e1518_config()
360 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in m88e1518_config()
362 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in m88e1518_config()
364 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in m88e1518_config()
366 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); in m88e1518_config()
368 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); in m88e1518_config()
372 phy_reset(phydev); in m88e1518_config()
374 genphy_config_aneg(phydev); in m88e1518_config()
375 genphy_restart_aneg(phydev); in m88e1518_config()
381 static int m88e1510_config(struct phy_device *phydev) in m88e1510_config() argument
384 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, in m88e1510_config()
388 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL, in m88e1510_config()
393 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, in m88e1510_config()
397 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, in m88e1510_config()
402 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); in m88e1510_config()
404 return m88e1518_config(phydev); in m88e1510_config()
408 static int m88e1118_config(struct phy_device *phydev) in m88e1118_config() argument
411 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); in m88e1118_config()
413 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); in m88e1118_config()
415 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); in m88e1118_config()
417 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); in m88e1118_config()
419 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1118_config()
421 return genphy_config_aneg(phydev); in m88e1118_config()
424 static int m88e1118_startup(struct phy_device *phydev) in m88e1118_startup() argument
429 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1118_startup()
431 ret = genphy_update_link(phydev); in m88e1118_startup()
435 return m88e1xxx_parse_status(phydev); in m88e1118_startup()
439 static int m88e1121_config(struct phy_device *phydev) in m88e1121_config() argument
444 genphy_config_aneg(phydev); in m88e1121_config()
447 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); in m88e1121_config()
448 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, in m88e1121_config()
451 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, in m88e1121_config()
454 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); in m88e1121_config()
457 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); in m88e1121_config()
458 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); in m88e1121_config()
464 static int m88e1145_config(struct phy_device *phydev) in m88e1145_config() argument
469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); in m88e1145_config()
470 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); in m88e1145_config()
471 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); in m88e1145_config()
472 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); in m88e1145_config()
474 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, in m88e1145_config()
477 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); in m88e1145_config()
478 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in m88e1145_config()
481 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); in m88e1145_config()
483 genphy_config_aneg(phydev); in m88e1145_config()
486 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1145_config()
488 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1145_config()
493 static int m88e1145_startup(struct phy_device *phydev) in m88e1145_startup() argument
497 ret = genphy_update_link(phydev); in m88e1145_startup()
501 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, in m88e1145_startup()
503 return m88e1xxx_parse_status(phydev); in m88e1145_startup()
507 static int m88e1149_config(struct phy_device *phydev) in m88e1149_config() argument
509 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); in m88e1149_config()
510 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1149_config()
511 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); in m88e1149_config()
512 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); in m88e1149_config()
513 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1149_config()
515 genphy_config_aneg(phydev); in m88e1149_config()
517 phy_reset(phydev); in m88e1149_config()
523 static int m88e1310_config(struct phy_device *phydev) in m88e1310_config() argument
528 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); in m88e1310_config()
529 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); in m88e1310_config()
531 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); in m88e1310_config()
534 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); in m88e1310_config()
535 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); in m88e1310_config()
537 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); in m88e1310_config()
540 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); in m88e1310_config()
541 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); in m88e1310_config()
543 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); in m88e1310_config()
546 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); in m88e1310_config()
548 return genphy_config_aneg(phydev); in m88e1310_config()
551 static int m88e1680_config(struct phy_device *phydev) in m88e1680_config() argument
561 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004); in m88e1680_config()
562 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27); in m88e1680_config()
564 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg); in m88e1680_config()
567 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd); in m88e1680_config()
568 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53); in m88e1680_config()
569 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d); in m88e1680_config()
570 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1680_config()
573 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); in m88e1680_config()
574 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030); in m88e1680_config()
575 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c); in m88e1680_config()
576 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc); in m88e1680_config()
577 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c); in m88e1680_config()
578 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c); in m88e1680_config()
579 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1680_config()
580 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in m88e1680_config()
582 res = genphy_config_aneg(phydev); in m88e1680_config()
587 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1680_config()
589 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1680_config()