11 #define AR803x_PHY_DEBUG_ADDR_REG	0x1d
12 #define AR803x_PHY_DEBUG_DATA_REG	0x1e
14 #define AR803x_DEBUG_REG_5		0x5
15 #define AR803x_RGMII_TX_CLK_DLY		0x100
17 #define AR803x_DEBUG_REG_0		0x0
18 #define AR803x_RGMII_RX_CLK_DLY		0x8000
22 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);  in ar8021_config()
23 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);  in ar8021_config()
26 	return 0;  in ar8021_config()
52 	return 0;  in ar8031_config()
59 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);  in ar8035_config()
60 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);  in ar8035_config()
61 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);  in ar8035_config()
62 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);  in ar8035_config()
63 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));  in ar8035_config()
65 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);  in ar8035_config()
66 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);  in ar8035_config()
67 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));  in ar8035_config()
72 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);  in ar8035_config()
74 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);  in ar8035_config()
79 		/* select debug reg 0 */  in ar8035_config()
80 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);  in ar8035_config()
82 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);  in ar8035_config()
90 	return 0;  in ar8035_config()
95 	.uid = 0x4dd040,
96 	.mask = 0x4ffff0,
105 	.uid = 0x4dd074,
106 	.mask = 0xffffffef,
115 	.uid = 0x4dd072,
116 	.mask = 0xffffffef,
129 	return 0;  in phy_atheros_init()