61 #define DSIZE     0x00000FFF
70 	ChipCmd = 0x00,
71 	ChipConfig = 0x04,
72 	EECtrl = 0x08,
73 	IntrMask = 0x14,
74 	IntrEnable = 0x18,
75 	TxRingPtr = 0x20,
76 	TxRingPtrHi = 0x24,
77 	TxConfig = 0x28,
78 	RxRingPtr = 0x30,
79 	RxRingPtrHi = 0x34,
80 	RxConfig = 0x38,
81 	PriQueue = 0x3C,
82 	RxFilterAddr = 0x48,
83 	RxFilterData = 0x4C,
84 	ClkRun = 0xCC,
85 	PCIPM = 0x44,
89 	ChipReset = 0x100,
90 	RxReset = 0x20,
91 	TxReset = 0x10,
92 	RxOff = 0x08,
93 	RxOn = 0x04,
94 	TxOff = 0x02,
95 	TxOn = 0x01
99 	LinkSts = 0x80000000,
100 	GigSpeed = 0x40000000,
101 	HundSpeed = 0x20000000,
102 	FullDuplex = 0x10000000,
103 	TBIEn = 0x01000000,
104 	Mode1000 = 0x00400000,
105 	T64En = 0x00004000,
106 	D64En = 0x00001000,
107 	M64En = 0x00000800,
108 	PhyRst = 0x00000400,
109 	PhyDis = 0x00000200,
110 	ExtStEn = 0x00000100,
111 	BEMode = 0x00000001,
116 	TxDrthMask	= 0x000000ff,
117 	TxFlthMask	= 0x0000ff00,
118 	TxMxdmaMask	= 0x00700000,
119 	TxMxdma_8	= 0x00100000,
120 	TxMxdma_16	= 0x00200000,
121 	TxMxdma_32	= 0x00300000,
122 	TxMxdma_64	= 0x00400000,
123 	TxMxdma_128	= 0x00500000,
124 	TxMxdma_256	= 0x00600000,
125 	TxMxdma_512	= 0x00700000,
126 	TxMxdma_1024	= 0x00000000,
127 	TxCollRetry	= 0x00800000,
128 	TxAutoPad	= 0x10000000,
129 	TxMacLoop	= 0x20000000,
130 	TxHeartIgn	= 0x40000000,
131 	TxCarrierIgn	= 0x80000000
135 	RxDrthMask	= 0x0000003e,
136 	RxMxdmaMask	= 0x00700000,
137 	RxMxdma_8	= 0x00100000,
138 	RxMxdma_16	= 0x00200000,
139 	RxMxdma_32	= 0x00300000,
140 	RxMxdma_64	= 0x00400000,
141 	RxMxdma_128	= 0x00500000,
142 	RxMxdma_256	= 0x00600000,
143 	RxMxdma_512	= 0x00700000,
144 	RxMxdma_1024	= 0x00000000,
145 	RxAcceptLenErr	= 0x04000000,
146 	RxAcceptLong	= 0x08000000,
147 	RxAcceptTx	= 0x10000000,
148 	RxStripCRC	= 0x20000000,
149 	RxAcceptRunt	= 0x40000000,
150 	RxAcceptErr	= 0x80000000,
155 	RxFilterEnable		= 0x80000000,
156 	AcceptAllBroadcast	= 0x40000000,
157 	AcceptAllMulticast	= 0x20000000,
158 	AcceptAllUnicast	= 0x10000000,
159 	AcceptPerfectMatch	= 0x08000000,
171 	DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
172 	DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
173 	DescSizeMask = 0xfff,
175 	DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
176 	DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
177 	DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
178 	DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
180 	DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
181 	DescRxDest = 0x01800000, DescRxLong = 0x00400000,
182 	DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
183 	DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
184 	DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
189 	MDIO_ShiftClk = 0x0040,
190 	MDIO_EnbOutput = 0x0020,
191 	MDIO_Data = 0x0010,
196 	BMCR = 0x00,
197 	BMSR = 0x01,
198 	PHYIDR1 = 0x02,
199 	PHYIDR2 = 0x03,
200 	ANAR = 0x04,
201 	KTCR = 0x09,
206 	Bmcr_Reset = 0x8000,
207 	Bmcr_Loop = 0x4000,
208 	Bmcr_Speed0 = 0x2000,
209 	Bmcr_AutoNegEn = 0x1000,	/*if set ignores Duplex, Speed[01] */
210 	Bmcr_RstAutoNeg = 0x0200,
211 	Bmcr_Duplex = 0x0100,
212 	Bmcr_Speed1 = 0x0040,
213 	Bmcr_Force10H = 0x0000,
214 	Bmcr_Force10F = 0x0100,
215 	Bmcr_Force100H = 0x2000,
216 	Bmcr_Force100F = 0x2100,
217 	Bmcr_Force1000H = 0x0040,
218 	Bmcr_Force1000F = 0x0140,
223 	anar_adv_100F = 0x0100,
224 	anar_adv_100H = 0x0080,
225 	anar_adv_10F = 0x0040,
226 	anar_adv_10H = 0x0020,
227 	anar_ieee_8023 = 0x0001,
232 	ktcr_adv_1000H = 0x0100,
233 	ktcr_adv_1000F = 0x0200,
309 	int card_number = 0;  in ns8382x_initialize()
312 	int i, idx = 0;  in ns8382x_initialize()
318 		if ((devno = pci_find_devices(supported, idx++)) < 0)  in ns8382x_initialize()
322 		iobase &= ~0x3;	/* 1: unused and 0:I/O Space Indicator */  in ns8382x_initialize()
324 		debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);  in ns8382x_initialize()
344 		memset(dev, 0, sizeof(*dev));  in ns8382x_initialize()
358 		if (tmp & (0x03 | 0x100)) {	/* D0 state, disable PME assertion */  in ns8382x_initialize()
359 			u32 newtmp = tmp & ~(0x03 | 0x100);  in ns8382x_initialize()
364 		for (i = 0; i < 3; i++) {  in ns8382x_initialize()
378 			if (phy1 == 0x2000) {	/*check for 83861/91 */  in ns8382x_initialize()
380 				if ((rev & ~(0x000f)) == 0x00005c50 ||  in ns8382x_initialize()
381 				    (rev & ~(0x000f)) == 0x00005c60) {  in ns8382x_initialize()
396 		mdio_write(dev, phyAddress, BMCR, 0x0);	/*restore */  in ns8382x_initialize()
416 			       ? "0" : "",  in ns8382x_initialize()
419 			       dev->enetaddr[0], dev->enetaddr[1],  in ns8382x_initialize()
431 		OUTL(dev, SavedClkRun & ~0x100, ClkRun);  in ns8382x_initialize()
437 		pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);  in ns8382x_initialize()
452 #define MDIO_EnbIn  (0)
464 	while (--bits >= 0) {  in mdio_sync()
475 	int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;  in mdio_read()
476 	int i, retval = 0;  in mdio_read()
479 	for (i = 15; i >= 0; i--) {  in mdio_read()
488 	for (i = 19; i > 0; i--) {  in mdio_read()
492 		    (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);  in mdio_read()
496 	return (retval >> 1) & 0xffff;  in mdio_read()
502 	int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;  in mdio_write()
506 	for (i = 31; i >= 0; i--) {  in mdio_write()
515 	for (i = 2; i > 0; i--) {  in mdio_write()
544 	OUTL(dev, SavedClkRun & ~0x100, ClkRun);  in ns8382x_init()
559 	    | TxCollRetry | TxMxdma_1024 | (0x1002);  in ns8382x_init()
560 	rx_config = RxMxdma_1024 | 0x20;  in ns8382x_init()
569 	OUTL(dev, 0x0, PriQueue);  in ns8382x_init()
589 	OUTL(dev, 0, IntrMask);  in ns8382x_reset()
590 	OUTL(dev, 0, IntrEnable);  in ns8382x_reset()
604 	for (i = 0; i < ETH_ALEN; i += 2) {  in ns8382x_init_rxfilter()
620 	txd.link = (u32) 0;  in ns8382x_init_txd()
621 	txd.bufptr = cpu_to_le32((u32) & txb[0]);  in ns8382x_init_txd()
622 	txd.cmdsts = (u32) 0;  in ns8382x_init_txd()
623 	txd.extsts = (u32) 0;  in ns8382x_init_txd()
625 	OUTL(dev, 0x0, TxRingPtrHi);  in ns8382x_init_txd()
643 	OUTL(dev, 0x0, RxRingPtrHi);  in ns8382x_init_rxd()
645 	cur_rx = 0;  in ns8382x_init_rxd()
646 	for (i = 0; i < NUM_RX_DESC; i++) {  in ns8382x_init_rxd()
651 				rxd[0]);  in ns8382x_init_rxd()
652 		rxd[i].extsts = cpu_to_le32((u32) 0x0);  in ns8382x_init_rxd()
678 	u32 rx_mode = 0x0;  in ns8382x_set_rx_mode()
679 	/*spec says RxFilterEnable has to be 0 for rest of  in ns8382x_set_rx_mode()
694 	int gig = 0;  in ns8382x_check_duplex()
695 	int hun = 0;  in ns8382x_check_duplex()
696 	int duplex = 0;  in ns8382x_check_duplex()
699 	duplex = (config & FullDuplex) ? 1 : 0;  in ns8382x_check_duplex()
700 	gig = (config & GigSpeed) ? 1 : 0;  in ns8382x_check_duplex()
701 	hun = (config & HundSpeed) ? 1 : 0;  in ns8382x_check_duplex()
704 	       " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",  in ns8382x_check_duplex()
739 	u32 i, status = 0;  in ns8382x_send()
740 	vu_long tx_stat = 0;  in ns8382x_send()
748 	txd.link = cpu_to_le32(0x0);  in ns8382x_send()
750 	txd.extsts = cpu_to_le32(0x0);  in ns8382x_send()
765 	for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {  in ns8382x_send()
789  *            0 if no packet was received.
798 	int retstat = 0;  in ns8382x_poll()
799 	int length = 0;  in ns8382x_poll()
814 		retstat = 0;  in ns8382x_poll()
827 		cur_rx = 0;  in ns8382x_poll()
845 	OUTL(dev, 0, IntrMask);  in ns8382x_disable()
846 	OUTL(dev, 0, IntrEnable);  in ns8382x_disable()