Lines Matching refs:mvpp2_write
1297 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) in mvpp2_write() function
1430 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1432 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1435 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1437 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1451 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1462 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1473 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); in mvpp2_prs_hw_inv()
1474 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), in mvpp2_prs_hw_inv()
1906 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); in mvpp2_prs_hw_port_init()
1912 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); in mvpp2_prs_hw_port_init()
1920 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); in mvpp2_prs_hw_port_init()
2228 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK); in mvpp2_prs_default_init()
2232 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); in mvpp2_prs_default_init()
2234 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
2236 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index); in mvpp2_prs_default_init()
2238 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); in mvpp2_prs_default_init()
2480 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); in mvpp2_cls_flow_write()
2481 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); in mvpp2_cls_flow_write()
2482 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); in mvpp2_cls_flow_write()
2483 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); in mvpp2_cls_flow_write()
2493 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); in mvpp2_cls_lookup_write()
2494 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); in mvpp2_cls_lookup_write()
2505 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); in mvpp2_cls_init()
2534 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); in mvpp2_cls_port_config()
2559 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2562 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), in mvpp2_cls_oversize_rxq_set()
2567 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); in mvpp2_cls_oversize_rxq_set()
2597 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
2600 mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG, in mvpp2_bm_pool_create()
2603 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
2607 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
2627 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
2659 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
2695 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); in mvpp2_bm_init()
2697 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); in mvpp2_bm_init()
2730 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
2767 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val); in mvpp2_bm_pool_put()
2775 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); in mvpp2_bm_pool_put()
2776 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); in mvpp2_bm_pool_put()
3727 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
3729 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
3734 mvpp2_write(port->priv, in mvpp2_defaults_set()
3741 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8); in mvpp2_defaults_set()
3746 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
3748 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
3751 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
3761 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
3775 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
3788 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
3810 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
3811 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
3824 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
3828 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
3873 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
3903 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
3929 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_pend_desc_num_get()
3949 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); in mvpp2_aggr_txq_pend_desc_add()
3995 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
4001 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
4010 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
4022 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
4091 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); in mvpp2_aggr_txq_init()
4092 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num); in mvpp2_aggr_txq_init()
4118 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
4121 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
4126 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
4127 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
4128 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
4174 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
4175 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
4176 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
4177 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
4203 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
4204 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma); in mvpp2_txq_init()
4205 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & in mvpp2_txq_init()
4207 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
4208 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
4212 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
4223 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
4229 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
4235 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
4238 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
4259 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); in mvpp2_txq_deinit()
4262 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
4263 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
4264 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
4274 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
4277 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4297 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
4323 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4334 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
4853 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); in mvpp2_conf_mbus_windows()
4854 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); in mvpp2_conf_mbus_windows()
4857 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); in mvpp2_conf_mbus_windows()
4865 mvpp2_write(priv, MVPP2_WIN_BASE(i), in mvpp2_conf_mbus_windows()
4869 mvpp2_write(priv, MVPP2_WIN_SIZE(i), in mvpp2_conf_mbus_windows()
4875 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); in mvpp2_conf_mbus_windows()
4886 mvpp2_write(priv, in mvpp2_rx_fifo_init()
4889 mvpp2_write(priv, in mvpp2_rx_fifo_init()
4893 mvpp2_write(priv, in mvpp2_rx_fifo_init()
4896 mvpp2_write(priv, in mvpp2_rx_fifo_init()
4900 mvpp2_write(priv, in mvpp2_rx_fifo_init()
4903 mvpp2_write(priv, in mvpp2_rx_fifo_init()
4908 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4910 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
4915 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, in mvpp2_rx_fifo_init()
4917 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); in mvpp2_rx_fifo_init()
4934 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
4942 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); in mvpp2_axi_init()
4957 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); in mvpp2_axi_init()
4958 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); in mvpp2_axi_init()
4961 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); in mvpp2_axi_init()
4962 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); in mvpp2_axi_init()
4963 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); in mvpp2_axi_init()
4964 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); in mvpp2_axi_init()
4967 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); in mvpp2_axi_init()
4968 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); in mvpp2_axi_init()
4974 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); in mvpp2_axi_init()
4975 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); in mvpp2_axi_init()
4982 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); in mvpp2_axi_init()
4989 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); in mvpp2_axi_init()
5055 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); in mvpp2_init()
5286 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_send()