Lines Matching refs:MVPP2_RXQ_CONFIG_REG

92 #define MVPP2_RXQ_CONFIG_REG(rxq)		(0x800 + 4 * (rxq))  macro
2727 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_long_pool_set()
2730 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_long_pool_set()
3758 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_defaults_set()
3761 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_defaults_set()
3773 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_ingress_enable()
3775 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_ingress_enable()
3786 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_ingress_disable()
3788 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_ingress_disable()
3896 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_offset_set()
3903 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_offset_set()