Lines Matching full:pe
1419 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
1423 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
1427 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
1430 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1432 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); in mvpp2_prs_hw_write()
1435 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
1437 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); in mvpp2_prs_hw_write()
1443 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_read() argument
1447 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_read()
1451 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1453 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_hw_read()
1455 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_hw_read()
1459 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1462 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_read()
1464 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_hw_read()
1494 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
1498 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; in mvpp2_prs_tcam_lu_set()
1499 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; in mvpp2_prs_tcam_lu_set()
1503 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
1509 pe->tcam.byte[enable_off] &= ~(1 << port); in mvpp2_prs_tcam_port_set()
1511 pe->tcam.byte[enable_off] |= 1 << port; in mvpp2_prs_tcam_port_set()
1515 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
1521 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; in mvpp2_prs_tcam_port_map_set()
1522 pe->tcam.byte[enable_off] &= ~port_mask; in mvpp2_prs_tcam_port_map_set()
1523 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_set()
1527 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
1531 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
1535 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
1539 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; in mvpp2_prs_tcam_data_byte_set()
1540 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; in mvpp2_prs_tcam_data_byte_set()
1544 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
1548 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; in mvpp2_prs_tcam_data_byte_get()
1549 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; in mvpp2_prs_tcam_data_byte_get()
1553 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
1556 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
1557 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
1561 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
1564 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); in mvpp2_prs_sram_bits_set()
1568 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
1571 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); in mvpp2_prs_sram_bits_clear()
1575 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
1587 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1589 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); in mvpp2_prs_sram_ri_update()
1591 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
1596 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
1608 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1610 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); in mvpp2_prs_sram_ai_update()
1612 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
1617 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
1624 bits = (pe->sram.byte[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
1625 (pe->sram.byte[ai_en_off] << (8 - ai_shift)); in mvpp2_prs_sram_ai_get()
1633 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
1638 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
1640 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
1646 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
1651 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1654 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
1658 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = in mvpp2_prs_sram_shift_set()
1662 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
1664 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
1667 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
1673 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
1679 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1682 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
1686 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1688 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); in mvpp2_prs_sram_offset_set()
1689 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1692 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1697 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
1699 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
1702 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
1704 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); in mvpp2_prs_sram_offset_set()
1706 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1711 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + in mvpp2_prs_sram_offset_set()
1716 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
1722 struct mvpp2_prs_entry *pe; in mvpp2_prs_flow_find() local
1725 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_flow_find()
1726 if (!pe) in mvpp2_prs_flow_find()
1728 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_flow_find()
1738 pe->index = tid; in mvpp2_prs_flow_find()
1739 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_flow_find()
1740 bits = mvpp2_prs_sram_ai_get(pe); in mvpp2_prs_flow_find()
1744 return pe; in mvpp2_prs_flow_find()
1746 kfree(pe); in mvpp2_prs_flow_find()
1774 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
1778 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1779 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1782 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_drop_all_set()
1783 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1784 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
1787 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
1790 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
1791 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
1794 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
1797 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
1801 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
1803 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
1809 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
1815 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1816 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_promisc_set()
1819 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_promisc_set()
1820 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1821 pe.index = MVPP2_PE_MAC_PROMISCUOUS; in mvpp2_prs_mac_promisc_set()
1824 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
1827 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, in mvpp2_prs_mac_promisc_set()
1831 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
1835 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
1838 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
1842 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
1844 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
1851 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_multi_set() local
1861 pe.index = index; in mvpp2_prs_mac_multi_set()
1862 mvpp2_prs_hw_read(priv, &pe); in mvpp2_prs_mac_multi_set()
1865 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_multi_set()
1866 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1867 pe.index = index; in mvpp2_prs_mac_multi_set()
1870 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_multi_set()
1873 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, in mvpp2_prs_mac_multi_set()
1877 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); in mvpp2_prs_mac_multi_set()
1880 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_multi_set()
1884 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_multi_set()
1887 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_multi_set()
1891 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_multi_set()
1893 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_multi_set()
1926 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
1930 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_def_flow_init()
1931 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1932 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1935 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
1938 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1939 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
1942 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1943 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
1950 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
1952 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mh_init()
1954 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
1955 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1956 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1958 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
1961 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
1964 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1965 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1973 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
1975 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_mac_init()
1978 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
1979 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1981 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
1983 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
1984 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
1987 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
1990 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1991 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
2003 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
2012 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2013 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2014 pe.index = tid; in mvpp2_prs_etype_init()
2016 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES); in mvpp2_prs_etype_init()
2018 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
2020 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
2021 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2025 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2026 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2027 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2028 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
2030 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2038 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2039 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2040 pe.index = tid; in mvpp2_prs_etype_init()
2042 mvpp2_prs_match_etype(&pe, 0, PROT_ARP); in mvpp2_prs_etype_init()
2045 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2046 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2047 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2050 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2055 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2056 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2057 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2058 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
2060 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2068 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2069 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2070 pe.index = tid; in mvpp2_prs_etype_init()
2072 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
2075 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2076 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2077 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2082 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2087 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2088 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2089 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2090 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
2094 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2102 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2103 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2104 pe.index = tid; in mvpp2_prs_etype_init()
2106 mvpp2_prs_match_etype(&pe, 0, PROT_IP); in mvpp2_prs_etype_init()
2107 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2112 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
2113 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2116 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_etype_init()
2119 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2124 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2125 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2126 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2127 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
2129 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2137 pe.index = tid; in mvpp2_prs_etype_init()
2140 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2141 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; in mvpp2_prs_etype_init()
2143 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
2148 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_etype_init()
2149 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_etype_init()
2150 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2154 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2155 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2156 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2157 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
2159 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2167 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2168 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2169 pe.index = tid; in mvpp2_prs_etype_init()
2171 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6); in mvpp2_prs_etype_init()
2174 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
2177 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
2178 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2181 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2185 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2186 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2187 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
2188 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
2190 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2193 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
2194 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2195 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
2198 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
2201 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
2202 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
2203 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2206 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
2211 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
2212 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
2213 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
2214 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
2216 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
2270 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2277 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2293 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_range_find() local
2296 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_range_find()
2297 if (!pe) in mvpp2_prs_mac_da_range_find()
2299 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_range_find()
2311 pe->index = tid; in mvpp2_prs_mac_da_range_find()
2312 mvpp2_prs_hw_read(priv, pe); in mvpp2_prs_mac_da_range_find()
2313 entry_pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_range_find()
2315 if (mvpp2_prs_mac_range_equals(pe, da, mask) && in mvpp2_prs_mac_da_range_find()
2317 return pe; in mvpp2_prs_mac_da_range_find()
2319 kfree(pe); in mvpp2_prs_mac_da_range_find()
2328 struct mvpp2_prs_entry *pe; in mvpp2_prs_mac_da_accept() local
2334 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, in mvpp2_prs_mac_da_accept()
2338 if (!pe) { in mvpp2_prs_mac_da_accept()
2358 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_mac_da_accept()
2359 if (!pe) in mvpp2_prs_mac_da_accept()
2361 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2362 pe->index = tid; in mvpp2_prs_mac_da_accept()
2365 mvpp2_prs_tcam_port_map_set(pe, 0); in mvpp2_prs_mac_da_accept()
2369 mvpp2_prs_tcam_port_set(pe, port, add); in mvpp2_prs_mac_da_accept()
2372 pmap = mvpp2_prs_tcam_port_map_get(pe); in mvpp2_prs_mac_da_accept()
2375 kfree(pe); in mvpp2_prs_mac_da_accept()
2378 mvpp2_prs_hw_inv(priv, pe->index); in mvpp2_prs_mac_da_accept()
2379 priv->prs_shadow[pe->index].valid = false; in mvpp2_prs_mac_da_accept()
2380 kfree(pe); in mvpp2_prs_mac_da_accept()
2385 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
2390 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
2395 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2397 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2401 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
2405 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2406 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2407 mvpp2_prs_hw_write(priv, pe); in mvpp2_prs_mac_da_accept()
2409 kfree(pe); in mvpp2_prs_mac_da_accept()
2438 struct mvpp2_prs_entry *pe; in mvpp2_prs_def_flow() local
2441 pe = mvpp2_prs_flow_find(port->priv, port->id); in mvpp2_prs_def_flow()
2444 if (!pe) { in mvpp2_prs_def_flow()
2452 pe = kzalloc(sizeof(*pe), GFP_KERNEL); in mvpp2_prs_def_flow()
2453 if (!pe) in mvpp2_prs_def_flow()
2456 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2457 pe->index = tid; in mvpp2_prs_def_flow()
2460 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2461 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
2464 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2467 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); in mvpp2_prs_def_flow()
2468 mvpp2_prs_hw_write(port->priv, pe); in mvpp2_prs_def_flow()
2469 kfree(pe); in mvpp2_prs_def_flow()