109 #define     MVPP2_PRS_PORT_LU_VAL(port, val)	((val) << ((port) * 4))  argument
112 #define     MVPP2_PRS_INIT_OFF_VAL(port, val)	((val) << (((port) % 4) * 8))  argument
115 #define     MVPP2_PRS_MAX_LOOP_VAL(port, val)	((val) << (((port) % 4) * 8))  argument
175 #define     MVPP2_PREF_BUF_THRESH(val)		((val) << 17)  argument
286 #define     MVPP2_BM_LOW_THRESH_VALUE(val)	((val) << \  argument
290 #define     MVPP2_BM_HIGH_THRESH_VALUE(val)	((val) << \  argument
1314 		u64 val = (u64)dma_addr;  in mvpp2_txdesc_dma_addr_set()  local
1562 				    int val)  in mvpp2_prs_sram_bits_set()
1569 				      int val)  in mvpp2_prs_sram_bits_clear()
1900 	u32 val;  in mvpp2_prs_hw_port_init()  local
2490 	u32 val;  in mvpp2_cls_lookup_write()  local
2529 	u32 val;  in mvpp2_cls_port_config()  local
2557 	u32 val;  in mvpp2_cls_oversize_rxq_set()  local
2577 	u32 val;  in mvpp2_bm_pool_create()  local
2622 	u32 val;  in mvpp2_bm_pool_bufsize_set()  local
2649 	u32 val;  in mvpp2_bm_pool_destroy()  local
2716 	u32 val, mask;  in mvpp2_rxq_long_pool_set()  local
2756 		u32 val = 0;  in mvpp2_bm_pool_put()  local
2893 	u32 val;  in mvpp2_port_mii_set()  local
2913 	u32 val;  in mvpp2_port_fc_adv_enable()  local
2922 	u32 val;  in mvpp2_port_enable()  local
2932 	u32 val;  in mvpp2_port_disable()  local
2942 	u32 val;  in mvpp2_port_periodic_xon_disable()  local
2952 	u32 val;  in mvpp2_port_loopback_set()  local
2971 	u32 val;  in mvpp2_port_reset()  local
2985 	u32 val;  in mvpp2_gmac_max_rx_size_set()  local
2999 	u32 val;  in gop_gmac_reset()  local
3019 	u32 val;  in gop_gpcs_mode_cfg()  local
3034 	u32 val;  in gop_bypass_clk_cfg()  local
3049 	u32 val, thresh;  in gop_gmac_sgmii2_5_cfg()  local
3091 	u32 val, thresh;  in gop_gmac_sgmii_cfg()  local
3129 	u32 val, thresh;  in gop_gmac_rgmii_cfg()  local
3167 	u32 val;  in gop_gmac_mode_cfg()  local
3203 	u32 val;  in gop_xlg_2_gig_mac_cfg()  local
3218 	u32 val;  in gop_gpcs_reset()  local
3233 	u32 val;  in gop_xpcs_mode()  local
3262 	u32 val;  in gop_mpcs_mode()  local
3287 	u32 val;  in gop_xlg_mac_mode_cfg()  local
3325 	u32 val;  in gop_xpcs_reset()  local
3341 	u32 val;  in gop_xlg_mac_reset()  local
3433 	u32 val;  in gop_xlg_mac_port_enable()  local
3483 	u32 val = 0;  in mvpp2_netc_cfg_create()  local
3501 static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)  in gop_netc_active_port()
3516 static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)  in gop_netc_mii_mode()
3531 static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)  in gop_netc_gop_reset()
3546 static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)  in gop_netc_gop_clock_logic_set()
3561 static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)  in gop_netc_port_rf_reset()
3577 					   u32 val)  in gop_netc_gbe_sgmii_mode_select()
3599 static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)  in gop_netc_bus_width_select()
3614 static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)  in gop_netc_sample_stages_timing()
3710 	int tx_port_num, val, queue, ptxq, lrxq;  in mvpp2_defaults_set()  local
3768 	u32 val;  in mvpp2_ingress_enable()  local
3781 	u32 val;  in mvpp2_ingress_disable()  local
3856 	u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));  in mvpp2_rxq_received()  local
3871 	u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);  in mvpp2_rxq_status_update()  local
3891 	u32 val;  in mvpp2_rxq_offset_set()  local
3927 	u32 val;  in mvpp2_txq_pend_desc_num_get()  local
3959 	u32 val;  in mvpp2_txq_sent_desc_proc()  local
3983 	u32	val, size, mtu;  in mvpp2_txp_max_tx_size_set()  local
4184 	u32 val;  in mvpp2_txq_init()  local
4272 	u32 val;  in mvpp2_txq_clean()  local
4317 	u32 val;  in mvpp2_cleanup_txqs()  local
4389 	u32 val;  in mvpp2_link_event()  local
4394 			u32 val;  in mvpp2_link_event()  local
4923 	int port, val;  in mvpp2_tx_fifo_init()  local
4940 	u32 val, rdval, wrval;  in mvpp2_axi_init()  local
4997 	u32 val;  in mvpp2_init()  local