Lines Matching refs:mvreg_write
424 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) in mvreg_write() function
467 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
473 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
499 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
519 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
546 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_pend_desc_add()
571 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); in mvneta_rxq_buf_size_set()
595 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); in mvneta_port_up()
604 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); in mvneta_port_up()
618 mvreg_write(pp, MVNETA_RXQ_CMD, in mvneta_port_down()
641 mvreg_write(pp, MVNETA_TXQ_CMD, in mvneta_port_down()
686 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_enable()
697 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_disable()
718 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); in mvneta_set_ucast_table()
735 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); in mvneta_set_special_mcast_table()
754 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); in mvneta_set_other_mcast_table()
773 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); in mvneta_defaults_set()
774 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); in mvneta_defaults_set()
775 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_defaults_set()
778 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_defaults_set()
779 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_defaults_set()
780 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_defaults_set()
781 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); in mvneta_defaults_set()
784 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); in mvneta_defaults_set()
790 mvreg_write(pp, MVNETA_CPU_MAP(cpu), in mvneta_defaults_set()
795 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); in mvneta_defaults_set()
796 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); in mvneta_defaults_set()
799 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); in mvneta_defaults_set()
801 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); in mvneta_defaults_set()
802 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); in mvneta_defaults_set()
805 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); in mvneta_defaults_set()
806 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); in mvneta_defaults_set()
810 mvreg_write(pp, MVNETA_ACC_MODE, val); in mvneta_defaults_set()
814 mvreg_write(pp, MVNETA_PORT_CONFIG, val); in mvneta_defaults_set()
817 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); in mvneta_defaults_set()
818 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); in mvneta_defaults_set()
829 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); in mvneta_defaults_set()
835 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); in mvneta_defaults_set()
870 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); in mvneta_set_ucast_addr()
885 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); in mvneta_mac_addr_set()
886 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); in mvneta_mac_addr_set()
911 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
916 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
1023 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); in mvneta_rxq_init()
1024 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); in mvneta_rxq_init()
1059 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); in mvneta_txq_init()
1060 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); in mvneta_txq_init()
1063 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); in mvneta_txq_init()
1064 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); in mvneta_txq_init()
1079 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); in mvneta_txq_deinit()
1080 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); in mvneta_txq_deinit()
1083 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); in mvneta_txq_deinit()
1084 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); in mvneta_txq_deinit()
1179 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_adjust_link()
1201 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_adjust_link()
1291 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK); in mvneta_bypass_mbus_windows()
1311 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); in mvneta_conf_mbus_windows()
1312 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); in mvneta_conf_mbus_windows()
1315 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); in mvneta_conf_mbus_windows()
1323 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | in mvneta_conf_mbus_windows()
1326 mvreg_write(pp, MVNETA_WIN_SIZE(i), in mvneta_conf_mbus_windows()
1333 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); in mvneta_conf_mbus_windows()
1342 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); in mvneta_port_power_up()
1351 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); in mvneta_port_power_up()
1355 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); in mvneta_port_power_up()
1368 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); in mvneta_port_power_up()
1461 mvreg_write(pp, MVNETA_SMI, smi_reg); in mvneta_mdio_read()
1516 mvreg_write(pp, MVNETA_SMI, smi_reg); in mvneta_mdio_write()
1550 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_start()
1553 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); in mvneta_start()