430 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)  in mvreg_read()  function
442 		mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));  in mvneta_mib_counters_clear()
483 	val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));  in mvneta_rxq_busy_desc_num_get()
566 	val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));  in mvneta_rxq_buf_size_set()
614 	val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;  in mvneta_port_down()
632 		val = mvreg_read(pp, MVNETA_RXQ_CMD);  in mvneta_port_down()
638 	val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;  in mvneta_port_down()
656 		val = mvreg_read(pp, MVNETA_TXQ_CMD);  in mvneta_port_down()
671 		val = mvreg_read(pp, MVNETA_PORT_STATUS);  in mvneta_port_down()
684 	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);  in mvneta_port_enable()
695 	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);  in mvneta_port_disable()
833 		val = mvreg_read(pp, MVNETA_UNIT_CONTROL);  in mvneta_defaults_set()
860 	unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));  in mvneta_set_ucast_addr()
926 	val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));  in mvneta_txq_sent_desc_num_get()
1164 			val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);  in mvneta_adjust_link()
1198 			u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);  in mvneta_adjust_link()
1344 	ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);  in mvneta_port_power_up()
1370 	while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &  in mvneta_port_power_up()
1419 		smi_reg = mvreg_read(pp, MVNETA_SMI);  in smi_wait_ready()
1468 		smi_reg = mvreg_read(pp, MVNETA_SMI);  in mvneta_mdio_read()
1479 	return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;  in mvneta_mdio_read()