Lines Matching +full:0 +full:x0007ffff
19 #define PHY_BASE_ADR 0x08 /* default phy base addr */
23 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
24 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
25 #define MRU_MASK 0xfff1ffff
26 #define PHYADR_MASK 0x0000001f
27 #define PHYREG_MASK 0x0000001f
28 #define QTKNBKT_DEF_VAL 0x3fffffff
29 #define QMTBS_DEF_VAL 0x000003ff
30 #define QTKNRT_DEF_VAL 0x0000fcff
31 #define RXUQ 0 /* Used Rx queue */
32 #define TXUQ 0 /* Used Rx queue */
60 #define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
92 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
93 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
96 #define ACCEPT_MAC_ADDR 0
102 #define RX_BUF_OFFSET 0x2
105 #define MVGBE_INTERFACE_GMII_MII 0
107 #define MVGBE_LINK_IS_DOWN 0
109 #define MVGBE_PORT_AT_HALF_DUPLEX 0
111 #define MVGBE_RX_FLOW_CTRL_DISD 0
113 #define MVGBE_GMII_SPEED_100_10 0
115 #define MVGBE_MII_SPEED_10 0
117 #define MVGBE_NO_TX 0
119 #define MVGBE_BYPASS_NO_ACTIVE 0
121 #define MVGBE_PORT_NOT_AT_PARTN_STT 0
123 #define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
127 #define MVGBE_UCAST_MOD_NRML 0
131 #define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
133 #define MVGBE_RX_BC_IF_IP 0
135 #define MVGBE_RX_BC_IF_ARP 0
138 #define MVGBE_CPTR_TCP_FRMS_DIS 0
140 #define MVGBE_CPTR_UDP_FRMS_DIS 0
149 #define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
151 #define MVGBE_PARTITION_DIS 0
153 #define MVGBE_TX_CRC_GENERATION_EN 0
158 #define MVGBE_RX_BURST_SIZE_1_64BIT 0
164 #define MVGBE_BLM_RX_BYTE_SWAP 0
166 #define MVGBE_BLM_TX_BYTE_SWAP 0
168 #define MVGBE_DESCRIPTORS_NO_SWAP 0
169 #define MVGBE_TX_BURST_SIZE_1_64BIT 0
176 #define MVGBE_SERIAL_PORT_DIS 0
179 #define MVGBE_DO_NOT_FORCE_LINK_PASS 0
180 #define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
182 #define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
184 #define MVGBE_ADV_NO_FLOW_CTRL 0
186 #define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
188 #define MVGBE_FORCE_BP_MODE_NO_JAM 0
191 #define MVGBE_FORCE_LINK_FAIL 0
194 #define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
195 #define MVGBE_DTE_ADV_0 0
197 #define MVGBE_MIIPHY_MAC_MODE 0
199 #define MVGBE_AUTO_NEG_NO_CHANGE 0
201 #define MVGBE_MAX_RX_PACKET_1518BYTE 0
208 #define MVGBE_CLR_EXT_LOOPBACK 0
210 #define MVGBE_SET_HALF_DUPLEX_MODE 0
212 #define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
213 #define MVGBE_SET_GMII_SPEED_TO_10_100 0
215 #define MVGBE_SET_MII_SPEED_TO_10 0
220 #define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
221 #define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
230 #define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
241 #define MVGBE_LC_ERROR 0
248 #define MVGBE_CRC_ERROR 0
254 #define MVGBE_TCP_FRAME_OVER_IP_V_4 0
272 #define MVGBE_TCP_FRAME 0
285 #define EBAR_TARGET_DRAM 0x00000000
286 #define EBAR_TARGET_DEVICE 0x00000001
287 #define EBAR_TARGET_CBS 0x00000002
288 #define EBAR_TARGET_PCI0 0x00000003
289 #define EBAR_TARGET_PCI1 0x00000004
290 #define EBAR_TARGET_CUNIT 0x00000005
291 #define EBAR_TARGET_AUNIT 0x00000006
292 #define EBAR_TARGET_GUNIT 0x00000007
296 #define EBAR_DRAM_CS0 0x00000000
297 #define EBAR_DRAM_CS1 0x00000000
298 #define EBAR_DRAM_CS2 0x00000000
299 #define EBAR_DRAM_CS3 0x00000000
301 #define EBAR_DRAM_CS0 0x00000E00
302 #define EBAR_DRAM_CS1 0x00000D00
303 #define EBAR_DRAM_CS2 0x00000B00
304 #define EBAR_DRAM_CS3 0x00000700
308 #define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
309 #define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
310 #define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
313 #define EBAR_DEVICE_DEVCS0 0x00001E00
314 #define EBAR_DEVICE_DEVCS1 0x00001D00
315 #define EBAR_DEVICE_DEVCS2 0x00001B00
316 #define EBAR_DEVICE_DEVCS3 0x00001700
317 #define EBAR_DEVICE_BOOTCS3 0x00000F00
320 #define EBAR_PCI_BYTE_SWAP 0x00000000
321 #define EBAR_PCI_NO_SWAP 0x00000100
322 #define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
323 #define EBAR_PCI_WORD_SWAP 0x00000300
324 #define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
325 #define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
326 #define EBAR_PCI_IO_SPACE 0x00000000
327 #define EBAR_PCI_MEMORY_SPACE 0x00000800
328 #define EBAR_PCI_REQ64_FORCE 0x00000000
329 #define EBAR_PCI_REQ64_SIZE 0x00001000
332 #define EWIN_ACCESS_NOT_ALLOWED 0
359 u8 pad1[0x080 - 0x00c - 4];
362 u8 pad2[0x094 - 0x084 - 4];
365 u8 pad3[0x0b0 - 0x098 - 4];
367 u8 pad3a[0x200 - 0x0b0 - 4];
369 u8 pad4[0x280 - 0x22c - 4];
373 u8 pad5[0x400 - 0x294 - 4];
377 u8 pad6[0x410 - 0x408 - 4];
390 u8 pad7[0x460 - 0x454 - 4];
395 u8 pad8[0x474 - 0x46c - 4];
402 u8 pad11[0x494 - 0x488 - 4];
404 u8 pad12[0x4bc - 0x494 - 4];
406 u8 pad13[0x4dc - 0x4bc - 4];
412 u8 pad14[0x60c - 0x4ec - 4];
417 u8 pad15[0x6c0 - 0x684 - 4];
419 u8 pad16[0x700 - 0x6dc - 4];
422 u8 pad17[0x7a8 - 0x780 - 4];
426 u8 pad19[0x7c0 - 0x7b8 - 4];
432 u8 pad21[0x3000 - 0x27d0 - 4];
434 u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
438 u8 pad23[0xe20c0 - 0x7360c - 4];