97 	MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);  in smi_reg_read()
142 		MVGBE_REG_WR(regs->phyadr, data);  in smi_reg_write()
174 	MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);  in smi_reg_write()
222 	MVGBE_REG_WR(regs->epap, access_prot_reg);  in set_access_control()
225 	MVGBE_REG_WR(regs->barsz[param->win].size,  in set_access_control()
229 	MVGBE_REG_WR(regs->barsz[param->win].bar,  in set_access_control()
233 		MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);  in set_access_control()
300 		MVGBE_REG_WR(regs->dfut[table_index], 0);  in port_init_mac_tables()
304 		MVGBE_REG_WR(regs->dfsmt[table_index], 0);  in port_init_mac_tables()
306 		MVGBE_REG_WR(regs->dfomt[table_index], 0);  in port_init_mac_tables()
346 		MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);  in port_uc_addr()
353 		MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);  in port_uc_addr()
373 	MVGBE_REG_WR(regs->macal, mac_l);  in port_uc_addr_set()
374 	MVGBE_REG_WR(regs->macah, mac_h);  in port_uc_addr_set()
420 	MVGBE_REG_WR(regs->ic, 0);  in mvgbe_init()
421 	MVGBE_REG_WR(regs->ice, 0);  in mvgbe_init()
423 	MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);  in mvgbe_init()
425 	MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);  in mvgbe_init()
432 	MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);  in mvgbe_init()
433 	MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);  in mvgbe_init()
434 	MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);  in mvgbe_init()
437 	MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);  in mvgbe_init()
438 	MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);  in mvgbe_init()
439 	MVGBE_REG_WR(regs->tqx[0].tqxtbc,  in mvgbe_init()
442 	MVGBE_REG_WR(regs->pmtu, 0);  in mvgbe_init()
445 	MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE  in mvgbe_init()
455 	MVGBE_REG_WR(regs->pmtu, 0);  in mvgbe_init()
458 	MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);  in mvgbe_init()
462 	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));  in mvgbe_init()
491 	MVGBE_REG_WR(regs->bare, 0x3f);  in mvgbe_halt()
505 	MVGBE_REG_WR(regs->ic, 0);  in mvgbe_halt()
506 	MVGBE_REG_WR(regs->ice, 0);  in mvgbe_halt()
507 	MVGBE_REG_WR(regs->pim, 0);  in mvgbe_halt()
508 	MVGBE_REG_WR(regs->peim, 0);  in mvgbe_halt()
559 	MVGBE_REG_WR(regs->tqc, (1 << TXUQ));  in mvgbe_send()