59 		0,
63 		0,
73 		0,
125 	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {  in fec_initialize()
130 		memset(dev, 0, sizeof(*dev));  in fec_initialize()
134 		if (i == 0)  in fec_initialize()
165 		if (retval < 0)  in fec_initialize()
182 	j = 0;  in fec_send()
198 	out_be32(&fecp->fec_x_des_active, 0x01000000);  in fec_send()
200 	j = 0;  in fec_send()
233 		if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {  in fec_recv()
239 			if ((rx[0] & 1) != 0 &&  in fec_recv()
240 			    memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&  in fec_recv()
252 		out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);  in fec_recv()
258 			rxIdx = 0;  in fec_recv()
266 		out_be32(&fecp->fec_r_des_active, 0x01000000);  in fec_recv()
278 #define	FEC_ECNTRL_PINMUX	0x00000004
279 #define FEC_ECNTRL_ETHER_EN	0x00000002
280 #define FEC_ECNTRL_RESET	0x00000001
282 #define FEC_RCNTRL_BC_REJ	0x00000010
283 #define FEC_RCNTRL_PROM		0x00000008
284 #define FEC_RCNTRL_MII_MODE	0x00000004
285 #define FEC_RCNTRL_DRT		0x00000002
286 #define FEC_RCNTRL_LOOP		0x00000001
288 #define FEC_TCNTRL_FDEN		0x00000004
289 #define FEC_TCNTRL_HBC		0x00000002
290 #define FEC_TCNTRL_GTS		0x00000001
300 	uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;  in fec_10Mbps()
313 	uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;  in fec_100Mbps()
366 	setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);  in fec_pin_init()
367 	clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);  in fec_pin_init()
370 	if (fecidx == 0) {  in fec_pin_init()
377 		setbits_be16(&immr->im_ioport.iop_papar, 0xf830);  in fec_pin_init()
378 		setbits_be16(&immr->im_ioport.iop_padir, 0x0830);  in fec_pin_init()
379 		clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);  in fec_pin_init()
381 		setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);  in fec_pin_init()
382 		clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);  in fec_pin_init()
384 		setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);  in fec_pin_init()
385 		clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);  in fec_pin_init()
387 		setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);  in fec_pin_init()
388 		setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);  in fec_pin_init()
389 		clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);  in fec_pin_init()
391 		clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);  in fec_pin_init()
396 		setbits_be16(&immr->im_ioport.iop_papar, 0x1000);  in fec_pin_init()
397 		clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);  in fec_pin_init()
399 		setbits_be16(&immr->im_ioport.iop_papar, 0xe810);  in fec_pin_init()
400 		setbits_be16(&immr->im_ioport.iop_padir, 0x0810);  in fec_pin_init()
401 		clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);  in fec_pin_init()
403 		setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);  in fec_pin_init()
404 		clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);  in fec_pin_init()
406 		setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);  in fec_pin_init()
407 		clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);  in fec_pin_init()
415 		out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);  in fec_pin_init()
416 		out_be16(&immr->im_ioport.iop_pddir, 0x1fff);  in fec_pin_init()
419 		out_be16(&immr->im_ioport.iop_papar, 0xBBFF);  in fec_pin_init()
420 		out_be16(&immr->im_ioport.iop_padir, 0x04F0);  in fec_pin_init()
421 		out_be16(&immr->im_ioport.iop_paodr, 0x0000);  in fec_pin_init()
423 		out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);  in fec_pin_init()
424 		out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);  in fec_pin_init()
425 		out_be16(&immr->im_cpm.cp_pbodr, 0x0000);  in fec_pin_init()
427 		out_be16(&immr->im_ioport.iop_pcpar, 0x0400);  in fec_pin_init()
428 		out_be16(&immr->im_ioport.iop_pcdir, 0x0080);  in fec_pin_init()
429 		out_be16(&immr->im_ioport.iop_pcso , 0x0D53);  in fec_pin_init()
430 		out_be16(&immr->im_ioport.iop_pcint, 0x0000);  in fec_pin_init()
432 		out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);  in fec_pin_init()
433 		out_be16(&immr->im_ioport.iop_pddir, 0x1C09);  in fec_pin_init()
435 		setbits_be32(&immr->im_ioport.utmode, 0x80);  in fec_pin_init()
446 		setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);  in fec_pin_init()
447 		setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);  in fec_pin_init()
448 		clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);  in fec_pin_init()
449 		setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);  in fec_pin_init()
451 		clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);  in fec_pin_init()
455 		setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);  in fec_pin_init()
456 		setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);  in fec_pin_init()
457 		clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);  in fec_pin_init()
459 		setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);  in fec_pin_init()
460 		setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);  in fec_pin_init()
461 		setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);  in fec_pin_init()
462 		clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);  in fec_pin_init()
464 		setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);  in fec_pin_init()
465 		clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);  in fec_pin_init()
487 	for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&  in fec_reset()
494 	return 0;  in fec_reset()
510 	if (efis->ether_index != 0)  in fec_init()
514 	if (fec_reset(fecp) < 0)  in fec_init()
519 	out_be32(&fecp->fec_imask, 0);  in fec_init()
523 	out_be32(&fecp->fec_ievent, 0xffc0);  in fec_init()
530 	out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |  in fec_init()
539 	out_be32(&fecp->fec_hash_table_high, 0xffffffff);  in fec_init()
540 	out_be32(&fecp->fec_hash_table_low, 0xffffffff);  in fec_init()
544 	out_be32(&fecp->fec_hash_table_high, 0);  in fec_init()
545 	out_be32(&fecp->fec_hash_table_low, 0);  in fec_init()
559 	rxIdx = 0;  in fec_init()
560 	txIdx = 0;  in fec_init()
570 	for (i = 0; i < PKTBUFSRX; i++) {  in fec_init()
572 		out_be16(&rtx->rxbd[i].cbd_datlen, 0);	/* Reset */  in fec_init()
582 	for (i = 0; i < TX_BUF_CNT; i++) {  in fec_init()
584 		out_be16(&rtx->txbd[i].cbd_datlen, 0);	/* Reset */  in fec_init()
598 	out_be32(&fecp->fec_x_cntrl, 0);  in fec_init()
602 	out_be32(&fecp->fec_fun_code, 0x78000000);  in fec_init()
609 	rxIdx = 0;  in fec_init()
610 	txIdx = 0;  in fec_init()
657 	out_be32(&fecp->fec_r_des_active, 0x01000000);  in fec_init()
661 	return 0;  in fec_init()
685 	for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&  in fec_halt()
694 	efis->initialized = 0;  in fec_halt()
702 #define mk_mii_read(ADDR, REG)	(0x60020000 | ((ADDR << 23) | \
703 						(REG & 0x1f) << 18))
705 #define mk_mii_write(ADDR, REG, VAL)	(0x50020000 | ((ADDR << 23) | \
706 						(REG & 0x1f) << 18) | \
707 						(VAL & 0xffff))
711 #define FEC_ENET_HBERR	((uint)0x80000000)	/* Heartbeat error */
712 #define FEC_ENET_BABR	((uint)0x40000000)	/* Babbling receiver */
713 #define FEC_ENET_BABT	((uint)0x20000000)	/* Babbling transmitter */
714 #define FEC_ENET_GRA	((uint)0x10000000)	/* Graceful stop complete */
715 #define FEC_ENET_TXF	((uint)0x08000000)	/* Full frame transmitted */
716 #define FEC_ENET_TXB	((uint)0x04000000)	/* A buffer was transmitted */
717 #define FEC_ENET_RXF	((uint)0x02000000)	/* Full frame received */
718 #define FEC_ENET_RXB	((uint)0x01000000)	/* A buffer was received */
719 #define FEC_ENET_MII	((uint)0x00800000)	/* MII interrupt */
720 #define FEC_ENET_EBERR	((uint)0x00400000)	/* SDMA bus error */
736 	cnt = 0;  in mii_send()
745 	return mii_reply & 0xffff;		/* data read from phy */  in mii_send()
759 	for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {  in mii_discover_phy()
768 		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {  in mii_discover_phy()
770 			if (phytype != 0xffff) {  in mii_discover_phy()
777 	if (phyaddr < 0)  in mii_discover_phy()
796 	if (fec_reset(fecp) < 0)  in __mii_init()
801 	out_be32(&fecp->fec_imask, 0);  in __mii_init()
805 	out_be32(&fecp->fec_ievent, 0xffc0);  in __mii_init()
820 	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)  in mii_init()
827  * FIXME: These routines are expected to return 0 on success, but mii_send
828  *	  does _not_ return an error code. Maybe 0xFFFF means error, i.e.
830  *	  For now always return 0.
837 	unsigned short value = 0;  in fec8xx_miiphy_read()
851 	return 0;  in fec8xx_miiphy_write()