41 #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
42 #define LPC32XX_ETH_RX_CTRL_UNUSED    0x7FFFF800
43 #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
54 #define RX_STAT_RXSIZE 0x000007FF
56 #define RX_STAT_ERRORS 0x1B800000
67 #define TX_CTRL_TXSIZE    0x000007FF
68 #define TX_CTRL_LAST      0x40000000
79 	/* MAC registers - 0x3106_0000 to 0x3106_01FC */
95 	u32 sa0;		/* Station address register 0 */
113 	u32 tsv0;		/* Transmit status vector register 0 */
120 	/* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
128 	/* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
139 #define MAC1_RECV_ENABLE        0x00000001
140 #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
141 #define MAC1_SOFT_RESET         0x00008000
143 #define MAC1_RESETS             0x0000CF00
146 #define MAC2_FULL_DUPLEX    0x00000001
147 #define MAC2_CRC_ENABLE     0x00000010
148 #define MAC2_PAD_CRC_ENABLE 0x00000020
151 #define SUPP_SPEED 0x00000100
154 #define MCFG_RESET_MII_MGMT     0x00008000
156 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
159 #define MADR_REG_MASK   0x0000001F
160 #define MADR_PHY_MASK   0x00001F00
161 #define MADR_REG_OFFSET 0
165 #define MIND_BUSY      0x00000001
168 #define COMMAND_RXENABLE      0x00000001
169 #define COMMAND_TXENABLE      0x00000002
170 #define COMMAND_PASSRUNTFRAME 0x00000040
171 #define COMMAND_RMII          0x00000200
172 #define COMMAND_FULL_DUPLEX   0x00000400
174 #define COMMAND_RESETS        0x00000038
177 #define STATUS_RXSTATUS 0x00000001
178 #define STATUS_TXSTATUS 0x00000002
181 #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
182 #define RXFILTERCTRL_ACCEPTPERFECT   0x00000020
227  * Returns 16bit phy register value, or 0xffff on error
232 	u16 data = 0;  in mii_reg_read()
263 		if (--timeout == 0)  in mii_reg_read()
267 	/* write 0 to the MII command register to finish the read */  in mii_reg_read()
268 	writel(0, &regs->mcmd);  in mii_reg_read()
270 	if (timeout == 0) {  in mii_reg_read()
286  * Returns 0 if write succeed, -EINVAL on bad parameters
322 		if (--timeout == 0)  in mii_reg_write()
326 	if (timeout == 0) {  in mii_reg_write()
335 	return 0;  in mii_reg_write()
341  * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
345 #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
371 		if (timeout-- == 0)  in lpc32xx_eth_send()
382 	writel(0, &bufs->tx_stat[tx_index].statusinfo);  in lpc32xx_eth_send()
389 	return 0;  in lpc32xx_eth_send()
405 		if (timeout-- == 0)  in lpc32xx_eth_recv()
425 	return 0;  in lpc32xx_eth_recv()
435 	writel((unsigned long) (dev->enetaddr[0] |  in lpc32xx_eth_write_hwaddr()
442 	return 0;  in lpc32xx_eth_write_hwaddr()
458 	/* Retries: 15 (0xF). Collision window: 57 (0x37). */  in lpc32xx_eth_init()
459 	writel(0x370F, &regs->clrt);  in lpc32xx_eth_init()
461 	/* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */  in lpc32xx_eth_init()
462 	writel(0x0012, &regs->ipgr);  in lpc32xx_eth_init()
474 		writel(0x15, &regs->ipgt);  in lpc32xx_eth_init()
476 		writel(0x12, &regs->ipgt);  in lpc32xx_eth_init()
483 		writel(0, &regs->supp);  in lpc32xx_eth_init()
486 	writel((unsigned long) (dev->enetaddr[0] |  in lpc32xx_eth_init()
494 	for (index = 0; index < TX_BUF_COUNT; index++) {  in lpc32xx_eth_init()
495 		bufs->tx_desc[index].control = 0;  in lpc32xx_eth_init()
496 		bufs->tx_stat[index].statusinfo = 0;  in lpc32xx_eth_init()
503 	for (index = 0; index < RX_BUF_COUNT; index++) {  in lpc32xx_eth_init()
507 		bufs->rx_stat[index].statusinfo = 0;  in lpc32xx_eth_init()
508 		bufs->rx_stat[index].statushashcrc = 0;  in lpc32xx_eth_init()
519 	writel(0xFFFF, &regs->intclear);  in lpc32xx_eth_init()
520 	writel(0, &regs->intenable);  in lpc32xx_eth_init()
532 	index = 0;  in lpc32xx_eth_init()
535 	return 0;  in lpc32xx_eth_init()
550 	return 0;  in lpc32xx_eth_halt()
591 	return 0;  in lpc32xx_eth_phylib_init()
641 	if (retval < 0)  in lpc32xx_eth_initialize()
645 	return 0;  in lpc32xx_eth_initialize()