Lines Matching defs:lpc32xx_eth_registers

78 struct lpc32xx_eth_registers {  struct
80 	u32 mac1;		/* MAC configuration register 1 */
81 	u32 mac2;		/* MAC configuration register 2 */
82 	u32 ipgt;		/* Back-to-back Inter-Packet Gap reg. */
83 	u32 ipgr;		/* Non-back-to-back IPG register */
84 	u32 clrt;		/* Collision Window / Retry register */
85 	u32 maxf;		/* Maximum Frame register */
86 	u32 supp;		/* Phy Support register */
87 	u32 test;
88 	u32 mcfg;		/* MII management configuration reg. */
89 	u32 mcmd;		/* MII management command register */
90 	u32 madr;		/* MII management address register */
91 	u32 mwtd;		/* MII management wite data register */
92 	u32 mrdd;		/* MII management read data register */
93 	u32 mind;		/* MII management indicators register */
94 	u32 reserved1[2];
95 	u32 sa0;		/* Station address register 0 */
96 	u32 sa1;		/* Station address register 1 */
97 	u32 sa2;		/* Station address register 2 */
98 	u32 reserved2[45];
100 	u32 command;
101 	u32 status;
102 	u32 rxdescriptor;
103 	u32 rxstatus;
104 	u32 rxdescriptornumber;	/* actually, number MINUS ONE */
105 	u32 rxproduceindex;	/* head of rx desc fifo */
106 	u32 rxconsumeindex;	/* tail of rx desc fifo */
107 	u32 txdescriptor;
108 	u32 txstatus;
109 	u32 txdescriptornumber;	/* actually, number MINUS ONE */
110 	u32 txproduceindex;	/* head of rx desc fifo */
111 	u32 txconsumeindex;	/* tail of rx desc fifo */
112 	u32 reserved3[10];
113 	u32 tsv0;		/* Transmit status vector register 0 */
114 	u32 tsv1;		/* Transmit status vector register 1 */
115 	u32 rsv;		/* Receive status vector register */
116 	u32 reserved4[3];
117 	u32 flowcontrolcounter;
118 	u32 flowcontrolstatus;
119 	u32 reserved5[34];
121 	u32 rxfilterctrl;
122 	u32 rxfilterwolstatus;
123 	u32 rxfilterwolclear;
124 	u32 reserved6;
125 	u32 hashfilterl;
126 	u32 hashfilterh;
127 	u32 reserved7[882];
129 	u32 intstatus;		/* Interrupt status register */
130 	u32 intenable;
131 	u32 intclear;
132 	u32 intset;
133 	u32 reserved8;
134 	u32 powerdown;
135 	u32 reserved9;