99 } ks_str, *ks;  variable
141  * @ks: The chip state
155  * @ks: The chip information
169 	ks_wrreg16(dev, KS_IER, ks->rc_ier);  in ks_enable_int()
186  * @ks: The chip information
197 	ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;  in ks_read_config()
204 		ks->bus_width = ENUM_BUS_8BIT;  in ks_read_config()
205 		ks->extra_byte = 1;  in ks_read_config()
207 		ks->bus_width = ENUM_BUS_16BIT;  in ks_read_config()
208 		ks->extra_byte = 2;  in ks_read_config()
210 		ks->bus_width = ENUM_BUS_32BIT;  in ks_read_config()
211 		ks->extra_byte = 4;  in ks_read_config()
217  * @ks: The device state.
274 	u32 r = ks->extra_byte & 0x1;  in ks_read_qmu()
275 	u32 w = ks->extra_byte - r;  in ks_read_qmu()
279 	ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);  in ks_read_qmu()
297 	ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);  in ks_read_qmu()
302 	struct type_frame_head *frame_hdr = ks->frame_head_info;  in ks_rcv()
305 	ks->frame_cnt = ks_rdreg16(dev, KS_RXFCTR) >> 8;  in ks_rcv()
308 	for (i = 0; i < ks->frame_cnt; i++) {  in ks_rcv()
316 	frame_hdr = ks->frame_head_info;  in ks_rcv()
317 	while (ks->frame_cnt--) {  in ks_rcv()
328 			ks_wrreg16(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));  in ks_rcv()
337  * @ks: The device state
383 	ks->rc_rxqcr = RXQCR_CMD_CNTL;  in ks_setup()
384 	ks_wrreg16(dev, KS_RXQCR, ks->rc_rxqcr);  in ks_setup()
408 	ks->rc_ier = 0x00;  in ks_setup_int()
414 	ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);  in ks_setup_int()
507 	ks->frame_head_info = fr_h_i;  in ks8851_mll_init()
518 	ks->txh.txw[0] = 0;  in ks_write_qmu()
519 	ks->txh.txw[1] = cpu_to_le16(len);  in ks_write_qmu()
523 	ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);  in ks_write_qmu()
525 	ks_outblk(dev, ks->txh.txw, 4);  in ks_write_qmu()
529 	ks_wrreg8(dev, KS_RXQCR, (ks->rc_rxqcr & ~RXQCR_SDA) & 0xff);  in ks_write_qmu()
615 	ks = &ks_str;  in ks8851_mll_initialize()