Lines Matching +full:rv1106 +full:- +full:cru
4 * SPDX-License-Identifier: GPL-2.0+
6 * Rockchip GMAC ethernet IP driver for U-Boot
40 #include <dt-bindings/clock/rk3288-cru.h>
105 pdata->tx_delay = tx_delay; in gmac_set_rgmii()
106 pdata->rx_delay = rx_delay; in gmac_set_rgmii()
108 ops->set_to_rgmii(pdata); in gmac_set_rgmii()
121 pdata->clock_input = true; in gmac_rockchip_ofdata_to_platdata()
123 pdata->clock_input = false; in gmac_rockchip_ofdata_to_platdata()
125 /* If phy-handle property is passed from DT, use it as the PHY */ in gmac_rockchip_ofdata_to_platdata()
126 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); in gmac_rockchip_ofdata_to_platdata()
129 pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); in gmac_rockchip_ofdata_to_platdata()
131 debug("Found phy-handle subnode\n"); in gmac_rockchip_ofdata_to_platdata()
132 pdata->integrated_phy = ofnode_read_bool(args.node, in gmac_rockchip_ofdata_to_platdata()
133 "phy-is-integrated"); in gmac_rockchip_ofdata_to_platdata()
136 if (pdata->integrated_phy) { in gmac_rockchip_ofdata_to_platdata()
137 ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); in gmac_rockchip_ofdata_to_platdata()
145 ret = reset_get_by_index(phydev, 0, &pdata->phy_reset); in gmac_rockchip_ofdata_to_platdata()
153 /* Check the new naming-style first... */ in gmac_rockchip_ofdata_to_platdata()
154 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); in gmac_rockchip_ofdata_to_platdata()
155 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); in gmac_rockchip_ofdata_to_platdata()
158 if (pdata->tx_delay == -ENOENT) in gmac_rockchip_ofdata_to_platdata()
159 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); in gmac_rockchip_ofdata_to_platdata()
160 if (pdata->rx_delay == -ENOENT) in gmac_rockchip_ofdata_to_platdata()
161 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); in gmac_rockchip_ofdata_to_platdata()
174 struct dw_eth_dev *priv = &dev->dw; in px30_gmac_fix_mac_speed()
185 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", in px30_gmac_fix_mac_speed()
190 switch (priv->phydev->speed) { in px30_gmac_fix_mac_speed()
204 debug("Unknown phy speed: %d\n", priv->phydev->speed); in px30_gmac_fix_mac_speed()
205 return -EINVAL; in px30_gmac_fix_mac_speed()
209 rk_clrsetreg(&grf->mac_con1, PX30_GMAC_SPEED_MASK, speed); in px30_gmac_fix_mac_speed()
217 struct dw_eth_dev *priv = &dev->dw; in rk1808_gmac_fix_mac_speed()
221 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", in rk1808_gmac_fix_mac_speed()
226 switch (priv->phydev->speed) { in rk1808_gmac_fix_mac_speed()
243 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rk1808_gmac_fix_mac_speed()
244 return -EINVAL; in rk1808_gmac_fix_mac_speed()
253 struct dw_eth_dev *priv = &dev->dw; in rk3228_gmac_fix_mac_speed()
272 switch (priv->phydev->speed) { in rk3228_gmac_fix_mac_speed()
274 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? in rk3228_gmac_fix_mac_speed()
279 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? in rk3228_gmac_fix_mac_speed()
287 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rk3228_gmac_fix_mac_speed()
288 return -EINVAL; in rk3228_gmac_fix_mac_speed()
292 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_fix_mac_speed()
304 struct dw_eth_dev *priv = &dev->dw; in rk3288_gmac_fix_mac_speed()
308 switch (priv->phydev->speed) { in rk3288_gmac_fix_mac_speed()
319 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rk3288_gmac_fix_mac_speed()
320 return -EINVAL; in rk3288_gmac_fix_mac_speed()
324 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); in rk3288_gmac_fix_mac_speed()
332 struct dw_eth_dev *priv = &dev->dw; in rk3308_gmac_fix_mac_speed()
343 ret = clk_get_by_name(priv->phydev->dev, "clk_mac_speed", in rk3308_gmac_fix_mac_speed()
348 switch (priv->phydev->speed) { in rk3308_gmac_fix_mac_speed()
362 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rk3308_gmac_fix_mac_speed()
363 return -EINVAL; in rk3308_gmac_fix_mac_speed()
367 rk_clrsetreg(&grf->mac_con0, RK3308_GMAC_SPEED_MASK, speed); in rk3308_gmac_fix_mac_speed()
375 struct dw_eth_dev *priv = &dev->dw; in rk3328_gmac_fix_mac_speed()
394 switch (priv->phydev->speed) { in rk3328_gmac_fix_mac_speed()
396 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? in rk3328_gmac_fix_mac_speed()
401 clk = (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) ? in rk3328_gmac_fix_mac_speed()
409 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rk3328_gmac_fix_mac_speed()
410 return -EINVAL; in rk3328_gmac_fix_mac_speed()
414 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], in rk3328_gmac_fix_mac_speed()
426 struct dw_eth_dev *priv = &dev->dw; in rk3368_gmac_fix_mac_speed()
436 switch (priv->phydev->speed) { in rk3368_gmac_fix_mac_speed()
447 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rk3368_gmac_fix_mac_speed()
448 return -EINVAL; in rk3368_gmac_fix_mac_speed()
452 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); in rk3368_gmac_fix_mac_speed()
460 struct dw_eth_dev *priv = &dev->dw; in rk3399_gmac_fix_mac_speed()
464 switch (priv->phydev->speed) { in rk3399_gmac_fix_mac_speed()
475 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rk3399_gmac_fix_mac_speed()
476 return -EINVAL; in rk3399_gmac_fix_mac_speed()
480 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); in rk3399_gmac_fix_mac_speed()
488 struct dw_eth_dev *priv = &dev->dw; in rv1108_set_rmii_speed()
500 switch (priv->phydev->speed) { in rv1108_set_rmii_speed()
510 debug("Unknown phy speed: %d\n", priv->phydev->speed); in rv1108_set_rmii_speed()
511 return -EINVAL; in rv1108_set_rmii_speed()
515 rk_clrsetreg(&grf->gmac_con0, in rv1108_set_rmii_speed()
525 struct eqos_priv *priv = &dev->eqos; in rk3528_set_rgmii_speed()
548 switch (priv->phy->speed) { in rk3528_set_rgmii_speed()
550 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) in rk3528_set_rgmii_speed()
551 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 : in rk3528_set_rgmii_speed()
557 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) in rk3528_set_rgmii_speed()
558 div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 : in rk3528_set_rgmii_speed()
564 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) in rk3528_set_rgmii_speed()
567 return -EINVAL; in rk3528_set_rgmii_speed()
570 debug("Unknown phy speed: %d\n", priv->phy->speed); in rk3528_set_rgmii_speed()
571 return -EINVAL; in rk3528_set_rgmii_speed()
574 if (pdata->bus_id) in rk3528_set_rgmii_speed()
575 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div); in rk3528_set_rgmii_speed()
577 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div); in rk3528_set_rgmii_speed()
585 struct eqos_priv *priv = &dev->eqos; in rk3562_set_gmac_speed()
615 switch (priv->phy->speed) { in rk3562_set_gmac_speed()
617 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { in rk3562_set_gmac_speed()
618 if (pdata->bus_id > 0) { in rk3562_set_gmac_speed()
620 rk_clrsetreg(&grf->soc_con[0], in rk3562_set_gmac_speed()
631 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) { in rk3562_set_gmac_speed()
632 if (pdata->bus_id > 0) { in rk3562_set_gmac_speed()
634 rk_clrsetreg(&grf->soc_con[0], in rk3562_set_gmac_speed()
645 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) in rk3562_set_gmac_speed()
648 return -EINVAL; in rk3562_set_gmac_speed()
651 debug("Unknown phy speed: %d\n", priv->phy->speed); in rk3562_set_gmac_speed()
652 return -EINVAL; in rk3562_set_gmac_speed()
655 if (pdata->bus_id) in rk3562_set_gmac_speed()
656 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div); in rk3562_set_gmac_speed()
658 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div); in rk3562_set_gmac_speed()
666 struct eqos_priv *priv = &dev->eqos; in rk3588_set_rgmii_speed()
683 switch (priv->phy->speed) { in rk3588_set_rgmii_speed()
685 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) in rk3588_set_rgmii_speed()
691 if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) in rk3588_set_rgmii_speed()
697 if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII) in rk3588_set_rgmii_speed()
700 return -EINVAL; in rk3588_set_rgmii_speed()
703 debug("Unknown phy speed: %d\n", priv->phy->speed); in rk3588_set_rgmii_speed()
704 return -EINVAL; in rk3588_set_rgmii_speed()
707 if (pdata->bus_id == 1) { in rk3588_set_rgmii_speed()
712 div <<= pdata->bus_id ? RK3588_GMAC1_ID_SHIFT : 0; in rk3588_set_rgmii_speed()
713 div_mask = pdata->bus_id ? (RK3588_GMAC_CLK_RGMII_DIV_MASK << 5) : in rk3588_set_rgmii_speed()
716 rk_clrsetreg(&php_grf->clk_con1, div_mask, div); in rk3588_set_rgmii_speed()
724 struct eqos_priv *priv = &dev->eqos; in rv1106_set_rmii_speed()
737 switch (priv->phy->speed) { in rv1106_set_rmii_speed()
745 debug("Unknown phy speed: %d\n", priv->phy->speed); in rv1106_set_rmii_speed()
746 return -EINVAL; in rv1106_set_rmii_speed()
749 rk_clrsetreg(&grf->gmac_clk_con, RV1106_GMAC_CLK_RMII_DIV_MASK, div); in rv1106_set_rmii_speed()
757 struct eqos_priv *priv = &dev->eqos; in rv1126_set_rgmii_speed()
761 ret = clk_get_by_name(priv->phy->dev, "clk_mac_speed", in rv1126_set_rgmii_speed()
769 switch ( priv->phy->speed) { in rv1126_set_rgmii_speed()
786 debug("Unknown phy speed: %d\n", priv->phy->speed); in rv1126_set_rgmii_speed()
787 return -EINVAL; in rv1126_set_rgmii_speed()
806 rk_clrsetreg(&grf->mac_con1, in px30_gmac_set_to_rmii()
836 rk_clrsetreg(&grf->mac_con1, in rk1808_gmac_set_to_rgmii()
844 rk_clrsetreg(&grf->mac_con0, in rk1808_gmac_set_to_rgmii()
847 (pdata->rx_delay << RK1808_CLK_RX_DL_CFG_GMAC_SHIFT) | in rk1808_gmac_set_to_rgmii()
848 (pdata->tx_delay << RK1808_CLK_TX_DL_CFG_GMAC_SHIFT)); in rk1808_gmac_set_to_rgmii()
879 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_set_to_rgmii()
888 rk_clrsetreg(&grf->mac_con[0], in rk3228_gmac_set_to_rgmii()
891 pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | in rk3228_gmac_set_to_rgmii()
892 pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); in rk3228_gmac_set_to_rgmii()
908 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_set_to_rmii()
922 rk_clrsetreg(&grf->soc_con1, in rk3288_gmac_set_to_rgmii()
926 rk_clrsetreg(&grf->soc_con3, in rk3288_gmac_set_to_rgmii()
933 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | in rk3288_gmac_set_to_rgmii()
934 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); in rk3288_gmac_set_to_rgmii()
948 rk_clrsetreg(&grf->mac_con0, in rk3308_gmac_set_to_rmii()
981 rk_clrsetreg(&grf->mac_con[1], in rk3328_gmac_set_to_rgmii()
990 rk_clrsetreg(&grf->mac_con[0], in rk3328_gmac_set_to_rgmii()
993 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | in rk3328_gmac_set_to_rgmii()
994 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); in rk3328_gmac_set_to_rgmii()
1009 rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], in rk3328_gmac_set_to_rmii()
1039 rk_clrsetreg(&grf->soc_con15, in rk3368_gmac_set_to_rgmii()
1043 rk_clrsetreg(&grf->soc_con16, in rk3368_gmac_set_to_rgmii()
1050 (pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT) | in rk3368_gmac_set_to_rgmii()
1051 (pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT)); in rk3368_gmac_set_to_rgmii()
1060 rk_clrsetreg(&grf->soc_con5, in rk3399_gmac_set_to_rgmii()
1064 rk_clrsetreg(&grf->soc_con6, in rk3399_gmac_set_to_rgmii()
1071 (pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT) | in rk3399_gmac_set_to_rgmii()
1072 (pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT)); in rk3399_gmac_set_to_rgmii()
1085 rk_clrsetreg(&grf->gmac_con0, in rv1108_gmac_set_to_rmii()
1118 rk_clrsetreg(&grf->con_iomux, in rk3228_gmac_integrated_phy_powerup()
1122 rk_clrsetreg(&grf->macphy_con[2], in rk3228_gmac_integrated_phy_powerup()
1126 rk_clrsetreg(&grf->macphy_con[3], in rk3228_gmac_integrated_phy_powerup()
1131 rk_clrsetreg(&grf->macphy_con[0], in rk3228_gmac_integrated_phy_powerup()
1139 reset_assert(&pdata->phy_reset); in rk3228_gmac_integrated_phy_powerup()
1141 reset_deassert(&pdata->phy_reset); in rk3228_gmac_integrated_phy_powerup()
1144 rk_clrsetreg(&grf->macphy_con[0], in rk3228_gmac_integrated_phy_powerup()
1178 rk_clrsetreg(&grf->macphy_con[1], in rk3328_gmac_integrated_phy_powerup()
1182 rk_clrsetreg(&grf->macphy_con[2], in rk3328_gmac_integrated_phy_powerup()
1186 rk_clrsetreg(&grf->macphy_con[3], in rk3328_gmac_integrated_phy_powerup()
1191 rk_clrsetreg(&grf->macphy_con[0], in rk3328_gmac_integrated_phy_powerup()
1199 reset_assert(&pdata->phy_reset); in rk3328_gmac_integrated_phy_powerup()
1201 reset_deassert(&pdata->phy_reset); in rk3328_gmac_integrated_phy_powerup()
1204 rk_clrsetreg(&grf->macphy_con[0], in rk3328_gmac_integrated_phy_powerup()
1248 node = dev_read_subnode(dev, "macphy-bgs"); in rk3528_gmac_integrated_phy_powerup()
1265 reset_assert(&pdata->phy_reset); in rk3528_gmac_integrated_phy_powerup()
1267 rk_clrsetreg(&grf->macphy_con0, in rk3528_gmac_integrated_phy_powerup()
1277 rk_clrsetreg(&grf->macphy_con1, in rk3528_gmac_integrated_phy_powerup()
1281 reset_deassert(&pdata->phy_reset); in rk3528_gmac_integrated_phy_powerup()
1304 if (pdata->bus_id == 1) { in rk3528_set_to_rmii()
1306 rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode); in rk3528_set_to_rmii()
1309 rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode); in rk3528_set_to_rmii()
1341 if (!pdata->bus_id) in rk3528_set_to_rgmii()
1346 if (pdata->rx_delay < 0) { in rk3528_set_to_rgmii()
1351 rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT; in rk3528_set_to_rgmii()
1354 rk_clrsetreg(&grf->gmac1_con0, in rk3528_set_to_rgmii()
1361 rk_clrsetreg(&grf->gmac1_con1, in rk3528_set_to_rgmii()
1364 (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) | in rk3528_set_to_rgmii()
1381 if (!pdata->bus_id) { in rk3562_set_to_rmii()
1383 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode); in rk3562_set_to_rmii()
1416 if (pdata->bus_id) in rk3562_set_to_rgmii()
1422 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK, in rk3562_set_to_rgmii()
1425 if (pdata->rx_delay < 0) { in rk3562_set_to_rgmii()
1430 rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT; in rk3562_set_to_rgmii()
1433 rk_clrsetreg(&ioc->mac0_io_con1, in rk3562_set_to_rgmii()
1438 rk_clrsetreg(&ioc->mac0_io_con0, in rk3562_set_to_rgmii()
1441 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | in rk3562_set_to_rgmii()
1444 rk_clrsetreg(&ioc->mac1_io_con1, in rk3562_set_to_rgmii()
1449 rk_clrsetreg(&ioc->mac1_io_con0, in rk3562_set_to_rgmii()
1452 (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) | in rk3562_set_to_rgmii()
1469 if (pdata->bus_id == 1) in rk3568_set_to_rmii()
1470 con1 = &grf->mac1_con1; in rk3568_set_to_rmii()
1472 con1 = &grf->mac0_con1; in rk3568_set_to_rmii()
1508 if (pdata->bus_id == 1) { in rk3568_set_to_rgmii()
1509 con0 = &grf->mac1_con0; in rk3568_set_to_rgmii()
1510 con1 = &grf->mac1_con1; in rk3568_set_to_rgmii()
1512 con0 = &grf->mac0_con0; in rk3568_set_to_rgmii()
1513 con1 = &grf->mac0_con1; in rk3568_set_to_rgmii()
1519 (pdata->rx_delay << RK3568_CLK_RX_DL_CFG_GMAC_SHIFT) | in rk3568_set_to_rgmii()
1520 (pdata->tx_delay << RK3568_CLK_TX_DL_CFG_GMAC_SHIFT)); in rk3568_set_to_rgmii()
1551 if (pdata->bus_id == 1) { in rk3588_set_to_rmii()
1563 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); in rk3588_set_to_rmii()
1564 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); in rk3588_set_to_rmii()
1608 if (pdata->rx_delay < 0) { in rk3588_set_to_rgmii()
1613 rx_delay = pdata->rx_delay << RK3588_CLK_RX_DL_CFG_GMAC_SHIFT; in rk3588_set_to_rgmii()
1616 if (pdata->bus_id == 1) { in rk3588_set_to_rgmii()
1617 offset_con = &grf->soc_con9; in rk3588_set_to_rgmii()
1627 offset_con = &grf->soc_con8; in rk3588_set_to_rgmii()
1640 (pdata->tx_delay << RK3588_CLK_TX_DL_CFG_GMAC_SHIFT) | in rk3588_set_to_rgmii()
1643 rk_clrsetreg(&grf->soc_con7, tx_enable_mask | rx_enable_mask, in rk3588_set_to_rgmii()
1646 rk_clrsetreg(&php_grf->gmac_con0, intf_sel_mask, intf_sel); in rk3588_set_to_rgmii()
1647 rk_clrsetreg(&php_grf->clk_con1, clk_mode_mask, clk_mode); in rk3588_set_to_rgmii()
1693 node = dev_read_subnode(dev, "macphy-bgs"); in rv1106_gmac_integrated_phy_powerup()
1710 reset_assert(&pdata->phy_reset); in rv1106_gmac_integrated_phy_powerup()
1712 rk_clrsetreg(&grf->macphy_con0, in rv1106_gmac_integrated_phy_powerup()
1722 rk_clrsetreg(&grf->macphy_con1, in rv1106_gmac_integrated_phy_powerup()
1726 reset_deassert(&pdata->phy_reset); in rv1106_gmac_integrated_phy_powerup()
1739 rk_clrsetreg(&grf->gmac_clk_con, in rv1106_set_to_rmii()
1756 rk_clrsetreg(&grf->mac_con0, in rv1126_set_to_rmii()
1803 rk_clrsetreg(&grf->mac_con0, in rv1126_set_to_rgmii()
1815 rk_clrsetreg(&grf->mac_con1, in rv1126_set_to_rgmii()
1818 (pdata->rx_delay << RV1126_M0_CLK_RX_DL_CFG_GMAC_SHIFT) | in rv1126_set_to_rgmii()
1819 (pdata->tx_delay << RV1126_M0_CLK_TX_DL_CFG_GMAC_SHIFT)); in rv1126_set_to_rgmii()
1821 rk_clrsetreg(&grf->mac_con2, in rv1126_set_to_rgmii()
1824 (pdata->rx_delay << RV1126_M1_CLK_RX_DL_CFG_GMAC_SHIFT) | in rv1126_set_to_rgmii()
1825 (pdata->tx_delay << RV1126_M1_CLK_TX_DL_CFG_GMAC_SHIFT)); in rv1126_set_to_rgmii()
1842 if (!pdata->bus_id) in rk3528_set_clock_selection()
1846 val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO : in rk3528_set_clock_selection()
1848 rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val); in rk3528_set_clock_selection()
1888 if (!pdata->bus_id) { in rk3562_set_clock_selection()
1889 val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO : in rk3562_set_clock_selection()
1891 rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val); in rk3562_set_clock_selection()
1892 val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO : in rk3562_set_clock_selection()
1894 rk_clrsetreg(&ioc->mac1_io_con1, in rk3562_set_clock_selection()
1896 rk_clrsetreg(&ioc->mac0_io_con1, in rk3562_set_clock_selection()
1900 val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO : in rk3562_set_clock_selection()
1902 rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val); in rk3562_set_clock_selection()
1903 val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO : in rk3562_set_clock_selection()
1905 rk_clrsetreg(&ioc->mac1_io_con1, in rk3562_set_clock_selection()
1923 val = pdata->clock_input ? RK3588_GMAC_CLK_SELET_IO : in rk3588_set_clock_selection()
1927 if (pdata->bus_id == 1) { in rk3588_set_clock_selection()
1932 rk_clrsetreg(&php_grf->clk_con1, mask, val); in rk3588_set_clock_selection()
1952 eth_pdata = &pdata->eth_pdata; in gmac_rockchip_probe()
1953 config = (struct eqos_config *)&ops->config; in gmac_rockchip_probe()
1955 eth_pdata->phy_interface = config->ops->eqos_get_interface(dev); in gmac_rockchip_probe()
1957 dw_pdata = &pdata->dw_eth_pdata; in gmac_rockchip_probe()
1958 eth_pdata = &dw_pdata->eth_pdata; in gmac_rockchip_probe()
1960 pdata->bus_id = dev->seq; in gmac_rockchip_probe()
1962 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in gmac_rockchip_probe()
1971 pdata->phy_interface = eth_pdata->phy_interface; in gmac_rockchip_probe()
1973 if (ops->set_clock_selection) in gmac_rockchip_probe()
1974 ops->set_clock_selection(pdata); in gmac_rockchip_probe()
1976 if (pdata->integrated_phy && ops->integrated_phy_powerup) in gmac_rockchip_probe()
1977 ops->integrated_phy_powerup(pdata); in gmac_rockchip_probe()
1979 switch (eth_pdata->phy_interface) { in gmac_rockchip_probe()
1988 if (!pdata->clock_input) { in gmac_rockchip_probe()
1991 return -EINVAL; in gmac_rockchip_probe()
1994 if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) in gmac_rockchip_probe()
1995 pdata->rx_delay = -1; in gmac_rockchip_probe()
1998 if (ops->set_to_rgmii) in gmac_rockchip_probe()
1999 ops->set_to_rgmii(pdata); in gmac_rockchip_probe()
2001 return -EPERM; in gmac_rockchip_probe()
2006 if (!pdata->clock_input) { in gmac_rockchip_probe()
2009 return -EINVAL; in gmac_rockchip_probe()
2013 if (ops->set_to_rmii) in gmac_rockchip_probe()
2014 ops->set_to_rmii(pdata); in gmac_rockchip_probe()
2019 return -ENXIO; in gmac_rockchip_probe()
2083 dw_pdata = &pdata->dw_eth_pdata; in gmac_rockchip_eth_start()
2084 eth_pdata = &dw_pdata->eth_pdata; in gmac_rockchip_eth_start()
2086 eth_pdata->enetaddr); in gmac_rockchip_eth_start()
2090 ret = ops->fix_mac_speed(pdata, priv); in gmac_rockchip_eth_start()
2217 { .compatible = "rockchip,px30-gmac",
2222 { .compatible = "rockchip,rk1808-gmac",
2227 { .compatible = "rockchip,rk3228-gmac",
2232 { .compatible = "rockchip,rk3288-gmac",
2237 { .compatible = "rockchip,rk3308-mac",
2242 { .compatible = "rockchip,rk3328-gmac",
2247 { .compatible = "rockchip,rk3368-gmac",
2252 { .compatible = "rockchip,rk3399-gmac",
2257 { .compatible = "rockchip,rv1108-gmac",
2262 { .compatible = "rockchip,rk3528-gmac",
2267 { .compatible = "rockchip,rk3562-gmac",
2272 { .compatible = "rockchip,rk3568-gmac",
2277 { .compatible = "rockchip,rk3588-gmac",
2282 { .compatible = "rockchip,rv1106-gmac",
2287 { .compatible = "rockchip,rv1126-gmac",