Lines Matching +full:tx +full:- +full:threshold
5 * Dante Su <dantesu@faraday-tech.com>
7 * SPDX-License-Identifier: GPL-2.0+
18 uint32_t txpd; /* 0x18: Tx Poll Demand Register */
20 uint32_t txba; /* 0x20: Tx Ring Base Address Register */
44 #define ISR_TXLOST (1 << 5) /* tx lost */
45 #define ISR_TXOK (1 << 4) /* tx to ethernet */
46 #define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
47 #define ISR_TXFIFO (1 << 2) /* tx to fifo */
58 #define MACCR_CRCAPD (1 << 14) /* tx crc append */
64 #define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
65 #define MACCR_TXEN (1 << 5) /* tx enable */
66 #define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
67 #define MACCR_LOOPBACK (1 << 3) /* loop-back */
70 #define MACCR_TXDMAEN (1 << 0) /* tx dma enable */
84 /* Tx Cycle Length */
87 /* Tx Threshold: Aggregate n interrupts as 1 interrupt */
89 /* Tx Interrupt Timeout = n * Tx Cycle */
94 /* Rx Threshold: Aggregate n interrupts as 1 interrupt */
106 /* Tx Cycle Length */
109 /* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
122 #define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
125 #define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */
164 #define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */
165 #define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */