89 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,  in fec_mdio_read()  argument
101 	writel(FEC_IEVENT_MII, &eth->ievent);  in fec_mdio_read()
106 			phy | reg, &eth->mii_data);  in fec_mdio_read()
110 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {  in fec_mdio_read()
118 	writel(FEC_IEVENT_MII, &eth->ievent);  in fec_mdio_read()
121 	val = (unsigned short)readl(&eth->mii_data);  in fec_mdio_read()
127 static void fec_mii_setspeed(struct ethernet_regs *eth)  in fec_mii_setspeed()  argument
150 	writel(speed << 1 | hold << 8, &eth->mii_speed);  in fec_mii_setspeed()
151 	debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));  in fec_mii_setspeed()
154 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,  in fec_mdio_write()  argument
165 		FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);  in fec_mdio_write()
169 	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {  in fec_mdio_write()
177 	writel(FEC_IEVENT_MII, &eth->ievent);  in fec_mdio_write()
202 	struct ethernet_regs *eth = fec->bus->priv;  in miiphy_restart_aneg()  local
209 	fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);  in miiphy_restart_aneg()
211 	fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);  in miiphy_restart_aneg()
215 	fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,  in miiphy_restart_aneg()
218 	fec_mdio_write(eth, fec->phy_id, MII_BMCR,  in miiphy_restart_aneg()
234 	struct ethernet_regs *eth = fec->bus->priv;  in miiphy_wait_aneg()  local
244 		status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);  in miiphy_wait_aneg()
259 	writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);  in fec_rx_task_enable()
270 	writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);  in fec_tx_task_enable()
376 	writel(0, &fec->eth->iaddr1);  in fecmxc_set_hwaddr()
377 	writel(0, &fec->eth->iaddr2);  in fecmxc_set_hwaddr()
378 	writel(0, &fec->eth->gaddr1);  in fecmxc_set_hwaddr()
379 	writel(0, &fec->eth->gaddr2);  in fecmxc_set_hwaddr()
383 	       &fec->eth->paddr1);  in fecmxc_set_hwaddr()
384 	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);  in fecmxc_set_hwaddr()
395 	writel(0x00000000, &fec->eth->imask);  in fec_reg_setup()
398 	writel(0xffffffff, &fec->eth->ievent);  in fec_reg_setup()
411 	writel(rcntrl, &fec->eth->r_cntrl);  in fec_reg_setup()
435 	writel(1 << 2, &fec->eth->x_cntrl);  in fec_open()
451 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,  in fec_open()
452 	       &fec->eth->ecntrl);  in fec_open()
454 	writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,  in fec_open()
455 	       &fec->eth->x_wmrk);  in fec_open()
458 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,  in fec_open()
459 	       &fec->eth->ecntrl);  in fec_open()
466 	writew(0, &fec->eth->miigsk_enr);  in fec_open()
469 	while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)  in fec_open()
473 	writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);  in fec_open()
476 	writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);  in fec_open()
480 	while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {  in fec_open()
510 		u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;  in fec_open()
511 		u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;  in fec_open()
516 		writel(ecr, &fec->eth->ecntrl);  in fec_open()
517 		writel(rcr, &fec->eth->r_cntrl);  in fec_open()
540 	uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;  in fecmxc_init()
562 	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */  in fecmxc_init()
563 	writel(0x2, &fec->eth->x_wmrk);  in fecmxc_init()
566 	writel(0x00000000, &fec->eth->gaddr1);  in fecmxc_init()
567 	writel(0x00000000, &fec->eth->gaddr2);  in fecmxc_init()
576 		writel(0x520, &fec->eth->r_fstart);  in fecmxc_init()
580 	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);  in fecmxc_init()
581 	writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);  in fecmxc_init()
582 	writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);  in fecmxc_init()
610 	writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),  in fecmxc_halt()
611 	       &fec->eth->x_cntrl);  in fecmxc_halt()
615 	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))  in fecmxc_halt()
626 	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,  in fecmxc_halt()
627 	       &fec->eth->ecntrl);  in fecmxc_halt()
739 		if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))  in fecmxc_send()
811 	ievent = readl(&fec->eth->ievent);  in fecmxc_recv()
812 	writel(ievent, &fec->eth->ievent);  in fecmxc_recv()
827 		writel(0x00000001 | readl(&fec->eth->x_cntrl),  in fecmxc_recv()
828 		       &fec->eth->x_cntrl);  in fecmxc_recv()
832 		if (readl(&fec->eth->x_cntrl) & 0x00000001) {  in fecmxc_recv()
838 			writel(~0x00000001 & readl(&fec->eth->x_cntrl),  in fecmxc_recv()
839 			       &fec->eth->x_cntrl);  in fecmxc_recv()
1000 	struct ethernet_regs *eth = priv->eth;  in fec_get_miibus()  local
1002 	struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;  in fec_get_miibus()
1014 	bus->priv = eth;  in fec_get_miibus()
1023 	fec_mii_setspeed(eth);  in fec_get_miibus()
1072 	fec->eth = (struct ethernet_regs *)base_addr;  in fec_probe()
1078 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);  in fec_probe()
1080 	while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {  in fec_probe()
1102 	/* only support one eth device, the index number pointed by dev_id */  in fec_probe()
1109 			sprintf(mac, "eth%daddr", fec->dev_id);  in fec_probe()
1240 	writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,  in fecmxc_probe()
1241 	       &priv->eth->ecntrl);  in fecmxc_probe()
1243 	while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {  in fecmxc_probe()
1263 		bus = fec_get_miibus((ulong)priv->eth, dev->seq);  in fecmxc_probe()
1313 	priv->eth = (struct ethernet_regs *)pdata->iobase;  in fecmxc_ofdata_to_platdata()