2  * Cirrus Logic EP93xx ethernet MAC / MII driver.
145  * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
150 	struct mac_regs *mac = GET_REGS(dev);  in ep93xx_mac_reset()  local
155 	value = readl(&mac->selfctl);  in ep93xx_mac_reset()
157 	writel(value, &mac->selfctl);  in ep93xx_mac_reset()
159 	while (readl(&mac->selfctl) & SELFCTL_RESET)  in ep93xx_mac_reset()
169 	struct mac_regs *mac = GET_REGS(dev);  in ep93xx_eth_open()  local
175 	/* Reset the MAC */  in ep93xx_eth_open()
196 	writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);  in ep93xx_eth_open()
197 	writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);  in ep93xx_eth_open()
198 	writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);  in ep93xx_eth_open()
200 	writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);  in ep93xx_eth_open()
201 	writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);  in ep93xx_eth_open()
202 	writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);  in ep93xx_eth_open()
204 	writel(0x00040000, &mac->txdthrshld);  in ep93xx_eth_open()
205 	writel(0x00040000, &mac->txststhrshld);  in ep93xx_eth_open()
207 	writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);  in ep93xx_eth_open()
208 	writel(BMCTL_TXEN, &mac->bmctl);  in ep93xx_eth_open()
215 	writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);  in ep93xx_eth_open()
216 	writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);  in ep93xx_eth_open()
217 	writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);  in ep93xx_eth_open()
219 	writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);  in ep93xx_eth_open()
220 	writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);  in ep93xx_eth_open()
221 	writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);  in ep93xx_eth_open()
223 	writel(0x00040000, &mac->rxdthrshld);  in ep93xx_eth_open()
225 	writel(BMCTL_RXEN, &mac->bmctl);  in ep93xx_eth_open()
227 	writel(0x00040000, &mac->rxststhrshld);  in ep93xx_eth_open()
230 	while (!(readl(&mac->bmsts) & BMSTS_RXACT))  in ep93xx_eth_open()
236 	 * status entries to the MAC.  in ep93xx_eth_open()
253 	writel(NUMRXDESC, &mac->rxdqenq);  in ep93xx_eth_open()
254 	writel(NUMRXDESC, &mac->rxstsqenq);  in ep93xx_eth_open()
256 	/* Set the primary MAC address */  in ep93xx_eth_open()
257 	writel(AFP_IAPRIMARY, &mac->afp);  in ep93xx_eth_open()
260 		&mac->indad);  in ep93xx_eth_open()
261 	writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);  in ep93xx_eth_open()
265 		RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);  in ep93xx_eth_open()
266 	writel(TXCTL_STXON, &mac->txctl);  in ep93xx_eth_open()
281  * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
286 	struct mac_regs *mac = GET_REGS(dev);  in ep93xx_eth_close()  local
290 	writel(0x00000000, &mac->rxctl);  in ep93xx_eth_close()
291 	writel(0x00000000, &mac->txctl);  in ep93xx_eth_close()
297  * Copy a frame of data from the MAC into the protocol layer for further
302 	struct mac_regs *mac = GET_REGS(dev);  in ep93xx_eth_rcv_packet()  local
353 		 * back to the MAC engine, and loop again, checking for  in ep93xx_eth_rcv_packet()
356 		writel(1, &mac->rxdqenq);  in ep93xx_eth_rcv_packet()
357 		writel(1, &mac->rxstsqenq);  in ep93xx_eth_rcv_packet()
372 	struct mac_regs *mac = GET_REGS(dev);  in ep93xx_eth_send_packet()  local
384 	 * to the MAC for transmission.  in ep93xx_eth_send_packet()
397 	writel(1, &mac->txdqenq);  in ep93xx_eth_send_packet()
440  * Initialize the EP93xx MAC.  The MAC hardware is reset.  Buffers are
442  * as well as for received packets.  The EP93XX MAC hardware is initialized.
559 	struct mac_regs *mac = (struct mac_regs *)MAC_BASE;  in ep93xx_miiphy_read()  local
571 	 * Save the current SelfCTL register value.  Set MAC to suppress  in ep93xx_miiphy_read()
575 	self_ctl = readl(&mac->selfctl);  in ep93xx_miiphy_read()
577 	writel(self_ctl & ~(1 << 8), &mac->selfctl);  in ep93xx_miiphy_read()
580 	while (readl(&mac->miists) & MIISTS_BUSY)  in ep93xx_miiphy_read()
588 		&mac->miicmd);  in ep93xx_miiphy_read()
589 	while (readl(&mac->miists) & MIISTS_BUSY)  in ep93xx_miiphy_read()
592 	value = (unsigned short)readl(&mac->miidata);  in ep93xx_miiphy_read()
595 	writel(self_ctl, &mac->selfctl);  in ep93xx_miiphy_read()
612 	struct mac_regs *mac = (struct mac_regs *)MAC_BASE;  in ep93xx_miiphy_write()  local
624 	 * Save the current SelfCTL register value.  Set MAC to suppress  in ep93xx_miiphy_write()
628 	self_ctl = readl(&mac->selfctl);  in ep93xx_miiphy_write()
630 	writel(self_ctl & ~(1 << 8), &mac->selfctl);  in ep93xx_miiphy_write()
633 	while (readl(&mac->miists) & MIISTS_BUSY)  in ep93xx_miiphy_write()
637 	writel((uint32_t)value, &mac->miidata);  in ep93xx_miiphy_write()
639 		&mac->miicmd);  in ep93xx_miiphy_write()
640 	while (readl(&mac->miists) & MIISTS_BUSY)  in ep93xx_miiphy_write()
644 	writel(self_ctl, &mac->selfctl);  in ep93xx_miiphy_write()