Lines Matching +full:auto +full:- +full:flow +full:- +full:control
4 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
7 * SPDX-License-Identifier: GPL-2.0+
11 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
41 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
52 writel((value), ((a)->hw_addr + E1000_##reg))
54 readl((a)->hw_addr + E1000_##reg)
56 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
58 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
135 /* Flow Control Settings */
328 Control and Address */
330 control register */
346 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
348 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
350 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
351 #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control
354 #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto
357 state of 100BASE-TX */
359 state of 10BASE-T */
360 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
364 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
366 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
374 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity
381 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
383 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
385 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
389 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
415 /* MAC decode size is 128K - This is the size of BAR0 */
436 (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
438 (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
481 * E1000_RAR_ENTRIES - 1 multicast addresses.
505 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
535 uint8_t cmd; /* Descriptor control */
684 * RW - register is both readable and writable
685 * RO - register is read only
686 * WO - register is write only
687 * R/clr - register is read only and is cleared when read
688 * A - register array
690 #define E1000_CTRL 0x00000 /* Device Control - RW */
691 #define E1000_STATUS 0x00008 /* Device Status - RO */
692 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
693 #define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */
694 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
695 #define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */
696 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
697 #define E1000_MDIC 0x00020 /* MDI Control - RW */
698 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
699 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
700 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
701 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
702 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
703 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
704 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
705 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
706 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
707 #define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */
708 #define E1000_RCTL 0x00100 /* RX Control - RW */
709 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
710 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
711 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
712 #define E1000_TCTL 0x00400 /* TX Control - RW */
713 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
714 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
715 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
716 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
717 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
718 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
720 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
721 #define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */
723 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
725 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
726 #define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */
728 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
730 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
731 #define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */
732 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
736 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
737 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
738 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
739 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
740 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
741 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
742 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
743 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
744 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
745 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
746 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
747 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
748 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
749 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
750 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
751 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
752 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
753 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
754 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
755 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
756 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
757 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
758 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
759 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
760 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
761 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
762 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
764 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
765 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
766 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
767 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
768 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
769 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
771 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
772 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
773 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
774 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
775 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
776 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
777 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
778 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
779 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
780 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
781 #define E1000_DC 0x04030 /* Defer Count - R/clr */
782 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
783 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
784 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
785 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
786 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
787 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
788 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
789 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
790 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
791 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
792 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
793 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
794 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
795 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
796 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
797 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
798 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
799 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
800 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
801 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
802 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
803 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
804 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
805 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
806 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
807 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
808 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
809 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
810 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
811 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
812 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
813 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
814 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
815 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
816 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
817 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
818 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
819 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
820 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
821 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
822 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
823 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
824 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
825 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
826 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
827 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
828 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
829 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
830 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
831 #define E1000_RA 0x05400 /* Receive Address - RW Array */
832 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
833 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
834 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
835 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
836 #define E1000_MANC 0x05820 /* Management Control - RW */
837 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
838 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
839 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
840 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
841 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
842 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
843 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
844 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1161 /* Device Control */
1168 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1170 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1187 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1188 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1205 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1209 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1210 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1211 #define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */
1213 /* Constants used to intrepret the masked PCI-X bus speed. */
1214 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1215 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1216 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1218 /* EEPROM/Flash Control */
1232 * (0-small, 1-large) */
1234 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1238 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1264 /* EEPROM Commands - Microwire */
1271 /* EEPROM Commands - SPI */
1275 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1310 /* Extended Device Control */
1345 /* MDI Control */
1363 /* LED Control */
1469 /* Receive Control */
1503 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1519 /* Flow Control */
1521 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1525 /* Receive Descriptor Control */
1532 /* Transmit Descriptor Control */
1551 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1552 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1561 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1563 /* Transmit Control */
1572 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1573 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1576 /* Receive Checksum Control */
1583 /* Wake Up Control */
1589 /* Wake Up Filter Control */
1621 /* Management Control */
1622 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1623 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1624 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1757 /* Flow Control Constants */
1762 /* The historical defaults for the flow control values are given below. */
1767 /* Flow Control High-Watermark: 43464 bytes */
1769 /* Flow Control Low-Watermark: 43456 bytes */
1771 /* Flow Control Pause Time: 858 usec */
1813 /* The number of milliseconds we wait for auto-negotiation to complete */
1841 * frame_length--;
1849 ((adapter)->tbi_compatibility_on && \
1853 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1854 ((length) <= ((adapter)->max_frame_size + 1))) : \
1855 (((length) > (adapter)->min_frame_size) && \
1856 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1861 * Clock (MDC) pins in the Device Control Register.
1874 #define PHY_CTRL 0x00 /* Control Register */
1883 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1884 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1888 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1892 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1898 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1919 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1926 /* IGP01E1000 AGC Registers - stores the cable length values*/
1932 /* IGP01E1000 Specific Port Config Register - R/W */
1947 non-D0a modes */
1973 /* IGP01E1000 PCS Initialization register - stores the polarity status when
1982 * on Link-Up */
2002 /* IGP01E1000 Specific Port Control Register - R/W */
2008 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2047 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
2062 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
2066 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
2068 /* PHY Specific Control Register 2 (Page 0, Register 26) */
2079 Auto-Negotiation */
2081 1000BASE-T */
2086 /* MAC Specific Control Register (Page 2, Register 21) */
2087 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2098 1 = 50-80M;
2099 2 = 80-110M;
2100 3 = 110-140M;
2103 /* Kumeran Mode Control Register (Page 193, Register 16) */
2113 /* Power Management Control Register (Page 193, Register 20) */
2119 Auto-Negotiation */
2121 Auto-Neg in non D0 */
2123 Auto-Neg Always */
2125 Reverse Auto-Negotiation */
2133 /* In-Band Control Register (Page 194, Register 18) */
2138 * 15-5: page
2139 * 4-0: register offset
2148 GG82563_REG(0, 16) /* PHY Specific Control */
2160 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2164 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2167 GG82563_REG(2, 21) /* MAC Specific Control Register */
2169 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2174 /* Page 193 - Port Control Registers */
2176 GG82563_REG(193, 16) /* Kumeran Mode Control */
2184 GG82563_REG(193, 20) /* Power Management Control */
2186 GG82563_REG(193, 25) /* Rate Adaptation Control */
2188 /* Page 194 - KMRN Registers */
2190 GG82563_REG(194, 16) /* FIFO's Control/Status */
2192 GG82563_REG(194, 17) /* Control */
2194 GG82563_REG(194, 18) /* Inband Control */
2210 /* PHY Control Register */
2214 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2217 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2226 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2228 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2265 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2298 /* 1000BASE-T Control Register */
2314 /* 1000BASE-T Status Register */
2338 /* M88E1000 PHY Specific Control Register */
2348 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2349 * 100BASE-TX/10BASE-T:
2352 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2356 /* 1=Enable Extended 10BASE-T distance
2357 * (Lower 10BASE-T RX Threshold)
2358 * 0=Normal 10BASE-T RX Threshold */
2360 /* 1=5-Bit interface in 100BASE-TX
2361 * 0=MII interface in 100BASE-TX */
2374 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2375 * 3=110-140M;4=>140M */
2389 /* M88E1000 Extended PHY Specific Control Register */
2394 * within 1ms in 1000BASE-T
2477 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
2506 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
2507 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
2508 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
2509 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
2510 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
2515 #define E1000_HICR 0x08F00 /* Host Inteface Control */
2523 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2542 /* FIFO Control */
2546 /* In-Band Control */
2550 /* Half-Duplex Control */
2566 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
2577 /* Extended Transmit Control */